Proceedings ArticleDOI
BEAM: bus encoding based on instruction-set-aware memories
Yazdan Aghaghiri,Farzan Fallah,Massoud Pedram +2 more
- pp 3-8
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TLDR
This paper introduces a new approach for minimizing power dissipation on the memory address bus that relies on the availability of smart memories that have certain awareness of the instruction format of one or more architectures.Abstract:
This paper introduces a new approach for minimizing power dissipation on the memory address bus. The proposed approach relies on the availability of smart memories that have certain awareness of the instruction format of one or more architectures. Based on this knowledge, the memory calculates or predicts the instruction and data addresses. Hence, not all addresses are sent from the processor to the memory. This, in turn, significantly reduces the activity on the memory bus. The proposed method can eliminate up to 97% of the transitions on the instruction address bus and 75% of the transitions on the data address bus with a small hardware overhead. The actual power savings of 85% for the instruction bus and 64% for the data bus were achieved for a per-line bus capacitance of 10 pF.read more
Citations
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Journal ArticleDOI
A survey of encoding techniques for reducing data-movement energy
Sparsh Mittal,Subhrajit Nag +1 more
TL;DR: A survey of encoding techniques for reducing data-movement energy by classifying the works on key metrics to bring out their similarities and differences in the area of interconnect and memory system design.
Journal Article
Power-efficient memory bus encoding using stride-based stream reconstruction
TL;DR: A bus encoding scheme, which may reduce transitions by reconstructing active address streams by obtaining the variable strides for dierent sets of active addressing streams such that the decoder reconstructs these interlaced streams with these strides.
Patent
Instruction address encoding and decoding based on program construct groups
TL;DR: In this article, an encoder is configured to encode an instruction address for transmission to a decoder, and the decoder is operative to identify the encoded instruction address as belonging to a particular one of a plurality of groups of instruction addresses associated with respective distinct program constructs.
Book ChapterDOI
Power Reduction Coding for Buses
TL;DR: Energy models of deep sub-micron buses, the coupling between energy and transmitted information, the ultimate limits of achievable power reduction using coding, a global theoretical framework of power reduction coding are presented.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Proceedings ArticleDOI
A study of branch prediction strategies
TL;DR: First, currently used techniques are discussed and analyzed using instruction trace data, and new techniques are proposed and are shown to provide greater accuracy and more flexibility at low cost.
Asymptotic zero-transition activity encoding for address buses in low-power microprocessor-based systems
TL;DR: Analytical and experimental analyses are presented showing the improved performance of the encoding scheme when compared to both binary and Gray addressing schemes, the latter being widely accepted as the most efficient method for address bus encoding.
Proceedings ArticleDOI
Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems
TL;DR: In this article, the authors propose an encoding scheme which is suitable for reducing the switching activity on the lines of an address bus, which relies on the observation that, in a remarkable number of cases, patterns traveling onto address buses are consecutive.