Binary adder architectures for cell-based VLSI and their synthesis
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It is found that the ripple-carry, the carry-lookahead, and the proposed carry-increment adders show the best overall performance characteristics for cell-based design.Abstract:
The addition of two binary numbers is the fundamental and most often used arithmetic operation on microprocessors, digital signal processors (DSP), and data-processing application-specific integrated circuits (ASIC). Therefore, bi¬ nary adders are crucial building blocks in very large-scale integrated (VLSI) circuits. Their efficient implementation is not trivial because a costly carrypropagation operation involving all operand bits has to be performed. Many different circuit architectures for binary addition have been proposed over the last decades, covering a wide range of performance characteristics. Also, their realization at the transistor level for full-custom circuit implemen¬ tations has been addressed intensively. However, the suitability of adder archi¬ tectures for cell-based design and hardware synthesis both prerequisites for the ever increasing productivity in ASIC design — was hardly investigated. Based on the various speed-up schemes for binary addition, a compre¬ hensive overview and a qualitative evaluation of the different existing adder architectures are given in this thesis. In addition, a new multilevel carryincrement adder architecture is proposed. It is found that the ripple-carry, the carry-lookahead, and the proposed carry-increment adders show the best overall performance characteristics for cell-based design. These three adder architectures, which together cover the entire range of possible area vs. delay trade-offs, are comprised in the more general prefix adder architecture reported in the literature. It is shown that this universal and flexible prefix adder structure also allows the realization of various customized adders and of adders fulfilling arbitrary timing and area constraints. A non-heuristic algorithm for the synthesis and optimization of prefix adders is proposed. It allows the runtime-efficient generation of area-optimal adders for given timing constraints.read more
Citations
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Bio-Inspired Imprecise Computational Blocks for Efficient VLSI Implementation of Soft-Computing Applications
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Efficient VLSI implementation of modulo (2/sup n//spl plusmn/1) addition and multiplication
TL;DR: It is shown that the parallel-prefix adder architecture is well suited to realize fast end-around-carry adders used for modulo addition, and a high-performance modulo multiplier-adder for the IDEA block cipher is presented.
Proceedings ArticleDOI
A taxonomy of parallel prefix networks
TL;DR: A three-dimensional taxonomy is presented that not only describes the tradeoffs in existing parallel prefix networks but also points to a family of new networks that are competitive in latency and area for some technologies.
Journal ArticleDOI
High-speed parallel-prefix module 2/sup n/-1 adders
TL;DR: A novel parallel-prefix architecture for high speed module 2/sup n/-1 adders is presented, based on the idea of recirculating the generate and propagate signals, instead of the traditional end-around carry approach.
Journal ArticleDOI
Diminished-one modulo 2/sup n/+1 adder design
TL;DR: In this paper, the authors present two new design methodologies for modulo 2/sup n/1 addition in the diminished-one number system, the first leads to carry look-ahead, whereas the second to parallel-prefix adder implementations.
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