Journal ArticleDOI
Characterizing, modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits
TLDR
This paper presents a symbolic framework to model soft errors in both synchronous and asynchronous designs, and is the first time that a decision diagram based soft error identification approach is proposed for asynchronous circuits.About:
This article is published in Microelectronics Reliability.The article was published on 2015-01-01. It has received 20 citations till now. The article focuses on the topics: Soft error & Asynchronous communication.read more
Citations
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Journal ArticleDOI
Effect of Current Density and Plating Time on Cu Electroplating in TSV and Low Alpha Solder Bumping
TL;DR: In this paper, a defectless, complete, and fast 100% Cu-filled TSV was achieved at cathodic and anodic current densities of −8 and 16μ/cm2 for a plating time of 4h, respectively.
Proceedings ArticleDOI
MASkIt: Soft error rate estimation for combinational circuits
TL;DR: Experimental results show that the proposed framework for SER estimation of combinational circuits reduces inaccuracy by 96% while adding minimal execution time overhead, and is two orders of magnitude faster than traditional Monte Carlo-based fault injection with minor loss in accuracy in both signal probability and SER estimation.
Proceedings ArticleDOI
Efficient and accurate analysis of single event transients propagation using SMT-based techniques
TL;DR: A new SET propagation model is proposed that simultaneously includes the impact of masking effects, width variation, and re-converging paths by utilizing satisfiability modulo theories and significantly enhances the efficiency of SET analysis.
Journal ArticleDOI
System-Level Analysis of the Vulnerability of Processors Exposed to Single-Event Upsets via Probabilistic Model Checking
TL;DR: A new system-level model of SEUs propagation through processors as a continuous-time Markov chain (CTMC) is presented, which can provide consistent results while being orders of magnitude faster in terms of CPU time.
Proceedings ArticleDOI
Efficient multilevel formal analysis and estimation of design vulnerability to Single Event Transients
TL;DR: Experimental results demonstrate that RASVAS is orders of magnitude faster than contemporary techniques and also handle designs as large as 256-bit adders while maintaining accuracy.
References
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Proceedings ArticleDOI
Modeling the effect of technology trends on the soft error rate of combinational logic
TL;DR: An end-to-end model is described and validated that enables us to compute the soft error rates (SER) for existing and future microprocessor-style designs and predicts that the SER per chip of logic circuits will increase nine orders of magnitude from 1992 to 2011 and at that point will be comparable to the SERper chip of unprotected memory elements.
Journal ArticleDOI
Fault injection for dependability validation: a methodology and some applications
Jean Arlat,M. Aguera,L. Amat,Yves Crouzet,Jean-Charles Fabre,Jean-Claude Laprie,Eliane Martins,David Powell +7 more
TL;DR: The authors address the problem of validating the dependability of fault-tolerant computing systems, in particular, the validation of the fault-Tolerance mechanisms through the use of fault injection at the physical level on a hardware/software prototype of the system considered.
Journal ArticleDOI
Unveiling the ISCAS-85 benchmarks: a case study in reverse engineering
TL;DR: The authors show how they reverse-engineered the ISCAS-85 benchmarks to add a useful, new high-level tool to the designer's arsenal.
Proceedings ArticleDOI
Practical design of globally-asynchronous locally-synchronous systems
TL;DR: This paper describes a complete design methodology for a globally asynchronous on-chip communication network connecting both locally-synchronous and asynchronous modules and confirmed the validity of the concept by applying it to an ASIC design implementing the Safer crypto-algorithm.
Proceedings ArticleDOI
FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs
TL;DR: Experimental results indicate that FASER achieves good accuracy compared to the SPICE-based simulation method, and can be further improved by more accurate cell library characterization.