Proceedings ArticleDOI
Code transformations for low power caching in embedded multimedia processors
Chidamber Kulkarni,F. Catthoor,H. De Man +2 more
- pp 292-297
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TLDR
This methodology rakes into account many program parameters like the locality of data, size of data structures, access structures of large array variables, regularity of loop nests and the size and type of cache with the objective of improving the cache performance for lower power.Abstract:
In this paper, we present several novel strategies to improve software controlled cache utilization, so as to achieve lower power requirements for multi-media and signal processing applications. Our methodology is targeted towards embedded multi-media and DSP processors. This methodology rakes into account many program parameters like the locality of data, size of data structures, access structures of large array variables, regularity of loop nests and the size and type of cache with the objective of improving the cache performance for lower power. We also take into account the potential overhead due to the different transformations on the instruction count and the number of execution cycles to meet the real time constraints and code size limitations. Experiments on a real life demonstrator illustrate the fact that our methodology is able to achieve significant gain in power requirements while meeting all other system constraints.read more
Citations
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Journal ArticleDOI
System-level power optimization: techniques and tools
Luca Benini,Giovanni De Micheli +1 more
TL;DR: This tutorial presents a cohesive view of power-conscious system-level design, which considers systems as consisting of a hardware platform executing software programs, and considers the major constituents of systems: processors, memories and communication resources.
Journal ArticleDOI
Data and memory optimization techniques for embedded systems
Preeti Ranjan Panda,Francky Catthoor,Nikil Dutt,Koen Danckaert,Erik Brockmeyer,Chidamber Kulkarni,A. Vandercappelle,Per Gunnar Kjeldsberg +7 more
TL;DR: A survey of the state-of-the-art techniques used in performing data and memory-related optimizations in embedded systems, covering a broad spectrum of optimization techniques that address memory architectures at varying levels of granularity.
Proceedings ArticleDOI
Power optimization of variable voltage core-based systems
TL;DR: The design methodology for the low power core-based real-time system-on-chip based on dynamically variable voltage hardware is developed, with the highlight of the proposed approach the non-preemptive scheduling heuristic which results in solutions very close to optimal ones for many test cases.
Journal ArticleDOI
Power optimization of variable-voltage core-based systems
TL;DR: This work developed the design methodology for the low-power core-based real-time SOC based on dynamically variable voltage hardware and proposes a nonpreemptive scheduling heuristic, which results in solutions very close to optimal ones for many test cases.
BookDOI
Data Access and Storage Management for Embedded Programmable Processors
Francky Catthoor,Koen Danckaert,Chidamber Kulkarni,Erik Brockmeyer,Per Gunnar Kjeldsberg,Tanja Van Achteren,Thierry Omnes +6 more
TL;DR: DTSE in Programmable Architectures and Related Compiler Work on Data Tranfer and Storage Management, and Automated Data Reuse Exploration Techniques.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Proceedings ArticleDOI
The cache performance and optimizations of blocked algorithms
TL;DR: It is shown that the degree of cache interference is highly sensitive to the stride of data accesses and the size of the blocks, and can cause wide variations in machine performance for different matrix sizes.
Book
Image and Video Compression Standards: Algorithms and Architectures
TL;DR: An introduction to the algorithms and architectures that form the underpinnings of the image and video compressions standards, including JPEG, H.261 and H.263, while fully addressing the architecturalconsiderations involved when implementing these standards.
Journal ArticleDOI
A loop transformation theory and an algorithm to maximize parallelism
Michael Wolf,Monica S. Lam +1 more
TL;DR: The loop transformation theory is applied to the problem of maximizing the degree of coarse- or fine-grain parallelism in a loop nest and it is shown that the maximum degree of parallelism can be achieved by transforming the loops into a nest of coarsest fullypermutable loop nests and wavefronting the fully permutable nests.