Journal ArticleDOI
Computation and communication refinement for multiprocessor SoC design: A system-level perspective
Radu Marculescu,Umit Y. Ogras,Nicholas H. Zamora +2 more
- Vol. 11, Iss: 3, pp 564-592
TLDR
The methodology the authors advocate consists of developing abstract application and platform models, followed by application mapping onto the target platform, and then optimizing the overall system via performance analysis, which is critical for optimizing the communication infrastructure in this multiprocessor setup.Abstract:
Continuous advancements in semiconductor technology enable the design of complex systems-on-chips (SoCs) composed of tens or hundreds of IP cores. At the same time, the applications that need to run on such platforms have become increasingly complex and have tight power and performance requirements. Achieving a satisfactory design quality under these circumstances is only possible when both computation and communication refinement are performed efficiently, in an automated and synergistic manner. Consequently, formal and disciplined system-level design methodologies are in great demand for future multiprocessor design. This article provides a broad overview of some fundamental research issues and state-of-the-art solutions concerning both computation and communication aspects of system-level design. The methodology we advocate consists of developing abstract application and platform models, followed by application mapping onto the target platform, and then optimizing the overall system via performance analysis. In addition, a communication refinement step is critical for optimizing the communication infrastructure in this multiprocessor setup. Finally, simulation and prototyping can be used for accurate performance evaluation purposes.read more
Citations
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Quo Vadis, SLD? Reasoning About the Trends and Challenges of System Level Design Recognizing common requirements for co-design of hardware and software in diverse systems may lead to productivity gains, lower costs and first-pass design success.
TL;DR: In this paper, the authors present the challenges faced by industry in system level design and propose a design methodology, platform-based design (PBD), that has the potential of addres- sing these challenges in a unified way.
Journal ArticleDOI
Quo Vadis, SLD? Reasoning About the Trends and Challenges of System Level Design
TL;DR: A design methodology, platform-based design (PBD), is proposed that has the potential of addressing system level design challenges in a unified way and a tool environment is presented, Metropolis, that supports PBD and can be used to integrate available tools and methods.
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Three-Dimensional Integrated Circuit Design
TL;DR: In this article, the first book on 3D integrated circuit design, covering all of the technological and design aspects of this emerging design paradigm, while proposing effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits.
Journal ArticleDOI
An Analytical Approach for Network-on-Chip Performance Analysis
TL;DR: The proposed model can be used not only to obtain fast and accurate performance estimates, but also to guide the NoC design process within an optimization loop.
Proceedings ArticleDOI
A case for heterogeneous on-chip interconnects for CMPs
TL;DR: This work proposes to apportion the resources in an NoC to leverage the non-uniformity in network resource demand, and results in a novel heterogeneous network, called HeteroNoC, which is composed of two types of routers - small power efficient routers, and big high performance routers.
References
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Proceedings ArticleDOI
Bandwidth-constrained mapping of cores onto NoC architectures
Srinivasan Murali,G. De Micheli +1 more
TL;DR: NMAP is presented, a fast algorithm that maps the cores onto a mesh NoC architecture under bandwidth constraints, minimizing the average communication delay, and the NMAP algorithm is presented for both single minimum-path routing and split-traffic routing.
Journal ArticleDOI
Energy- and performance-aware mapping for regular NoC architectures
Jingcao Hu,Radu Marculescu +1 more
TL;DR: An algorithm which automatically maps a given set of intellectual property onto a generic regular network-on-chip (NoC) architecture and constructs a deadlock-free deterministic routing function such that the total communication energy is minimized.
Book ChapterDOI
Networks on chip
Axel Jantsch,Hannu Tenhunen +1 more
TL;DR: There is a growing interest in Networks on Chips (NoC) that is related to the evolution of integrated circuit technology and to the growing requirements in performance and portability of electronic systems.
Journal ArticleDOI
Algebra of communicating processes with abstraction
Jan A. Bergstra,Jan Willem Klop +1 more
TL;DR: The system is an extension of ACP, Algebra of Communicating Processes, with Milner's τ-laws and an explicit abstraction operator, and syntactic properties such as consistency and conservativity over ACP are proved.
Book
Embedded Multiprocessors: Scheduling and Synchronization
TL;DR: This work presents architectures and design methodologies for parallel systems in embedded DSP applications, and describes unique techniques for optimizing communication and synchronization.