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Journal ArticleDOI

Computation and communication refinement for multiprocessor SoC design: A system-level perspective

TLDR
The methodology the authors advocate consists of developing abstract application and platform models, followed by application mapping onto the target platform, and then optimizing the overall system via performance analysis, which is critical for optimizing the communication infrastructure in this multiprocessor setup.
Abstract
Continuous advancements in semiconductor technology enable the design of complex systems-on-chips (SoCs) composed of tens or hundreds of IP cores. At the same time, the applications that need to run on such platforms have become increasingly complex and have tight power and performance requirements. Achieving a satisfactory design quality under these circumstances is only possible when both computation and communication refinement are performed efficiently, in an automated and synergistic manner. Consequently, formal and disciplined system-level design methodologies are in great demand for future multiprocessor design. This article provides a broad overview of some fundamental research issues and state-of-the-art solutions concerning both computation and communication aspects of system-level design. The methodology we advocate consists of developing abstract application and platform models, followed by application mapping onto the target platform, and then optimizing the overall system via performance analysis. In addition, a communication refinement step is critical for optimizing the communication infrastructure in this multiprocessor setup. Finally, simulation and prototyping can be used for accurate performance evaluation purposes.

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Citations
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A system-level approach to fault and variation resilience in multi-core die

TL;DR: This work investigates core sparing and network routing, and demonstrates that core sparing reduces the die cost asymptotically from O(A3) to O( Ah), and it is more cost efficient than larger design guard-bands of layout and circuit redundancy.

Abstraction-Based Performance Analysis of NoCs

TL;DR: This work gives an automatic technique to infer a traffic model, comprising formal models of sources and sinks, from simulation traces derived from software benchmarks, and demonstrates that the inferred models generalize well and can accurately verify industrial-scale NoC designs.
Proceedings ArticleDOI

Multiple V dd on 3D NoC architectures

TL;DR: A new methodology for power-efficient application mapping onto 3D NoC-based devices by clustering into the same router, IP cores with similar communication demands, it is possible to achieve reasonable energy savings while meeting timing constraints.
Proceedings ArticleDOI

Counterexample-guided SMT-driven optimal buffer sizing

TL;DR: This paper presents a new approach for minimizing the cumulative buffer size in on-chip networks, so as to meet throughput and latency requirements, given high-level specifications on traffic behavior.
Journal ArticleDOI

Influence of traffic correlation on the performance of network-on-chip designs

TL;DR: Experimental results show that traffic correlation degrades the performance of NoC design and unrealistic traffic assumptions may yield unacceptable designs.
References
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Book

Communication and Concurrency

TL;DR: This chapter discusses Bisimulation and Observation Equivalence as a Modelling Communication, a Programming Language, and its application to Equational laws.
Book

Data networks

TL;DR: Undergraduate and graduate classes in computer networks and wireless communications; undergraduate classes in discrete mathematics, data structures, operating systems and programming languages.
Journal ArticleDOI

Networks on chips: a new SoC paradigm

TL;DR: Focusing on using probabilistic metrics such as average values or variance to quantify design objectives such as performance and power will lead to a major change in SoC design methodologies.
Book

Statistics for long-memory processes

TL;DR: Theorems of Stationary Processes with Long Memory Limit Theorems and Estimations of Long Memory-Heuristic Approaches, Forecasting Regression Goodness of Fit Tests, and Robust Estimation of Long memory estimates are presented.
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