System-level modelling and design space exploration for multiprocessor embedded system-on-chip architectures

TLDR: This study targets such multiprocessor embedded systems and strives to develop algorithms, methods, and tools to deal with a number of fundamental problems which are encountered by the system designers during the early design stages.

Abstract: Modern embedded systems come with contradictory design constraints. On one hand, these systems often target mass production and battery-based devices, and therefore should be cheap and power efficient. On the other hand, they still need to show high (sometimes real-time) performance, and often support multiple applications and standards which requires high programmability. This wide spectrum of design requirements leads to complex heterogeneous System-on-Chip (SoC) architectures -- consisting of several types of processors from fully programmable microprocessors to configurable processing cores and customized hardware components, integrated on a single chip. This study targets such multiprocessor embedded systems and strives to develop algorithms, methods, and tools to deal with a number of fundamental problems which are encountered by the system designers during the early design stages.

Figures

Figure 2.13: Obtaining low level numbers.

Table 6.1: Task system specifications.

Figure 3.11: Notched boxplots showing the distribution of D-metric values for reciprocal comparison of MOEAs. Each nondominated set of a MOEA is compared with respect to each nondominated set from the other, and the resulting 900 comparisons is plotted. The plots are given for the JPEG decoder case study in ascending number of generations (50, 100, 200, 300, 500, and 1000) in the order from left to right and top to bottom. Hence, the top leftmost plot corresponds to MOEA comparisons with N = 50, while the bottom rightmost is for comparisons with N = 1000. The abbreviations s1, s2, n1, n2 are used in places of SPEA2R, SPEA2r, NSGA-IIR, NSGA-IIr, respectively. Comparisons regarding SPEA2 and NSGA-II are not given as they fail to converge (Section 3.4.1). Since D-metric is non-symmetric, i.e. D(Z1, Z2) 6= D(Z2, Z1), both comparisons are performed. Note that smaller values are always better.

Table 5.1: Parameters for processor and memory elements Processor Processing cap. Power cons. Cost

Table 5.1: Parameters for processor and memory elements Processor Processing cap. Power cons. Cost

Figure 4.8: (a) Refining blocks to lines. (b) Composite SDF actors in Sesame which exchange tokens with the architecture model.

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System-level modelling and design space exploration for multiprocessor
embedded system-on-chip architectures
Erbas, C.
Publication date
2006
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Erbas, C. (2006).
System-level modelling and design space exploration for multiprocessor
embedded system-on-chip architectures
. Amsterdam University Press.
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for-multiprocessor-embedded-system-on-chip-architectures.html
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Download date:10 Aug 2022

System-Level Modeling and
Design Space Exploration for
Multiprocessor Embedded
System-on-Chip Architectures
Çag˘kan Erbas¸
Modern embedded systems come with contradictory design constraints. On one hand, these sys-
tems often target mass production and battery-based devices, and therefore should be cheap and
power efficient. On the other hand, they still need to show high (sometimes real-time) perform-
ance, and often support multiple applications and standards, which require high programmability.
This wide spectrum of design requirements leads to complex heterogeneous System-on-Chip (SoC)
architectures – consisting of several types of processors from fully programmable microprocessors
to configurable processing cores and customized hardware components, integrated on a single
chip.This study targets such multiprocessor embedded systems and strives to develop algorithms,
methods, and tools to deal with a number of fundamental problems, which are encountered by
the system designers during the early design stages.
™xHSTAPGy294557z
Çag˘kan Erbas¸ received the BSc degree in electrical engineering from Middle East Technical
University, Ankara and the MSc degree in computer engineering from Ege University, Izmir.
He completed this PhD thesis at the University of Amsterdam in 2006. His research interests
include embedded systems, hardware/software codesign, multiobjective search algorithms
and meta-heuristics.
Çag˘kan Erbas¸System-Level Modeling and Design Space Exploration …
UvA Thesis
Faculty of Science
UNIVERSITEIT VAN AMSTERDAM
AUP/Erbas 10-10-2006 11:18 Pagina 1

System-Level Modeling and
Design Space Exploration for
Multiprocessor Embedded
System-on-Chip Architectures

Cover design: Ren´e Staelenberg, Amsterdam
Cover illustration: “Binary exploration” by C¸ a˘gkan Erbas¸
NUR 980
ISBN 90-5629-455-5
ISBN-13 978-90-5629-455-7
c
° Vossiuspers UvA – Amsterdam University Press, 2006
All rights reserved. Without limiting the rights under copyright reserved above, no
part of this book may be reproduced, stored in or introduced into a retrieval system,
or transmitted, in any form or by any means (electronic, mechanical, photocopying,
recording or otherwise) without the written permission of both the copyright owner
and the author of the book.

System-Level Modeling and
Design Space Exploration for
Multiprocessor Embedded
System-on-Chip Architectures
ACADEMISCH PROEFSCHRIFT
ter verkrijging van de graad van doctor
aan de Universiteit van Amsterdam,
op gezag van Rector Magnificus,
prof. mr. P. F. van der Heijden
ten overstaan van een door het College voor Promoties ingestelde
commissie, in het openbaar te verdedigen in de Aula der Universiteit
op donderdag 30 november 2006, te 13.00 uur
door
C¸ a
˘
gkan Erbas¸
geboren te K¨utahya, Turkije

Frequently asked questions

Q1. what is the meaning of the thesis?

Token exchange mechanism in Sesame 80 4.3.4 IDF actors for conditional code and loops 814.4 Dataflow actors for event refinement 83 4.5 Trace refinement experiment 86 4.6 Conclusion 905.1 Sesame: Pruning, exploration, and refinement 94 5.2 Artemis: Calibration and validation 101 5.3 Conclusion 1056.1 Problem definition 108 6.2 Recurring real-time task model 1106.2.1 Demand bound and request bound functions 111 6.2.2 Computing request bound function 1136.3 Schedulability under static priority scheduling 114 6.4 Dynamic priority scheduling 117 6.5 Simulated annealing framework 118 6.6 Experimental results 120 6.7 Conclusion 123 

Q2. What was the main topic of the lunch?

Of course, all the important stuff that you don’t want to miss like football, playstation, cars, women were being discussed during the lunch. 

Q3. What is the purpose of this paper?

This study targets such multiprocessor embedded systems and strives to develop algorithms, methods, and tools to deal with a number of fundamental problems, which are encountered by the system designers during the early design stages. 

Q4. What are the main constraints of multiprocessor embedded systems?

On one hand, these systems often target mass production and battery-based devices, and therefore should be cheap and power efficient. 

Q5. What are the main topics of this article?

Download date:10 Aug 2022System-Level Modeling and Design Space Exploration for Multiprocessor Embedded System-on-Chip ArchitecturesÇağkan ErbaşModern embedded systems come with contradictory design constraints. 

Q6. What is the title of the book?

Erbaş received the BSc degree in electrical engineering from Middle East Technical University, Ankara and the MSc degree in computer engineering from Ege University, Izmir.