Configuration compression for the Xilinx XC6200 FPGA

TLDR: An algorithm is developed, targeted to the decompression hardware imbedded in the Xilinx XC6200 series FPGA architecture, that can radically reduce the amount of data needed to transfer during reconfiguration, resulting in an overall reduction of almost 4 in total bandwidth required for reconfigurations.

Abstract: One of the major overheads in reconfigurable computing is the time it takes to reconfigure the devices in the system This overhead limits the speedups possible in this exciting new paradigm In this paper we explore one technique for reducing this overhead: the compression of configuration datastreams We develop an algorithm, targeted to the decompression hardware imbedded in the Xilinx XC6200 series FPGA architecture, that can radically reduce the amount of data needed to transfer during reconfiguration This results in an overall reduction of almost 4 in total bandwidth required for reconfiguration