Design methodology for a tightly coupled VLIW/reconfigurable matrix architecture: a case study
Bingfeng Mei,Serge Vernalde,Diederik Verkest,Rudy Lauwereins +3 more
- Vol. 2, pp 21224-21224
TLDR
A C-based design flow using an MPEG-2 decoder as a design example shows that the methodology and architecture can deliver a competitive package in terms of design efforts and performance over other programmable architectures.Abstract:
Coarse-grained reconfigurable architectures have seen growing importance recently. Design tools and methodology are essential to their success. Based on our previous work on modulo scheduling algorithms and a novel architecture with tightly coupled VLIW/reconfigurable matrix, we present a C-based design flow using an MPEG-2 decoder as a design example. The application is mapped to the architecture in less than one person-week starting from a software implementation. The kernel and overall speedup over the reference VLIW are 4.84 and 3.05 respectively. The case study shows that our methodology and architecture can deliver a competitive package in terms of design efforts and performance over other programmable architectures.read more
Citations
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A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH
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TL;DR: An overview of reconfigurable computing in embedded systems, in terms of benefits it can provide, how it has already been used, design issues, and hurdles that have slowed its adoption are presented.
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A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH
TL;DR: This paper explores the design and implementation of BORPH, an operating system designed for FPGA-based reconfigurable computers, and a Simulink-based design flow that integrates with BOR PH is employed.
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EPIMap: using epimorphism to map applications on CGRAs
TL;DR: Experimental results on 14 important kernels extracted from well known benchmark programs show that using EPIMap can improve the performance of the kernels on CGRA by more than 2.8X on average, as compared to one of the best existing mapping algorithm, EMS.
Proceedings ArticleDOI
Custom implementation of the coarse-grained reconfigurable ADRES architecture for multimedia purposes
TL;DR: The purpose of this study is to use the coarse-grained architecture for H264/AVC in order to determine at the physical level whether reconfigurable computing, high-performance and low-power can be obtained.
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