Design of a fully-static differential low-power CMOS flip-flop
Tolga Yalcin,N. Ismailoglu +1 more
- Vol. 1, pp 331-333
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TLDR
A fully-static flip-flop structure is proposed and compared to both the conventional CMOS flip- flop and the Cascode Voltage Switch Logic (CVSL) static flip-Flop proposed by Yuan and Svensson in terms of speed, power consumption and silicon area.Abstract:
A fully-static flip-flop structure is proposed and compared to both the conventional CMOS flip-flop and the Cascode Voltage Switch Logic (CVSL) static flip-flop proposed by Yuan and Svensson (see IEEE Jour. of Solid-State Circuits, vol. 32, no. 1, p. 62-9, 1997) in terms of speed, power consumption and silicon area. Then an add-and-delay circuit is implemented using all three flip-flop structures to demonstrate the performance of the proposed flip-flop. The add-and-delay structure is chosen since it is a widely used block in digital signal processing. The proposed structure is shown to consume less power and occupy a smaller silicon area. It has the additional advantage of being easier to merge with pass-transistor logic structures.read more
Citations
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A Variation-Aware Robust Gated Flip-Flop for Power-Constrained FSM Application
TL;DR: This paper has presented a novel low-pow design methodologies for long-term battery life solutions for smartphones and tablets that combine low power and high efficiency.
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Low-Power Flip-Flops: Survey, Comparative Evaluation, and a New Design
Ahmed Sayed,Hussain Al-Asaad +1 more
Proceedings ArticleDOI
Comparative analysis of low power high performance flipflops in the 0.13µm technology
TL;DR: A comparative analysis of existing architecture for flip-flops along with proposed designs is made and the proposed designs have better power delay product than the existing architectures and also occupy lesser area.
Survey and Evaluation of Low-Power Flip-Flops.
Ahmed Sayed,Hussain Al-Asaad +1 more
TL;DR: Survey a set of flip-flops designed for low power and high performance and evaluate them based on timing characteristics, power consumption, and other metrics.
Proceedings ArticleDOI
A low-power system-on-chip for telecommunications: single chip digital FM receiver/demodulator IP
Tolga Yalcin,N. Ismailoglu +1 more
TL;DR: Simulations showed that the designed single chip digital FM receiver/demodulator system has a performance comparable to those of ideal non-coherent FM demodulators, and would have a power dissipation very close to its analog counterparts when implemented with standard cells.
References
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Book
Application-Specific Integrated Circuits
TL;DR: This book provides the first comprehensive introduction to Application Specific Integrated Circuits (ASICs) with a focus on semi-custom technology.
Journal ArticleDOI
New single-clock CMOS latches and flipflops with improved speed and power savings
Jiren Yuan,Christer Svensson +1 more
TL;DR: In the new differential flipflops, clock loads are minimized and logic-related transistors are purely n-type in both n- and p-latches, giving additional speed advantage to this kind of CMOS circuits.
Journal ArticleDOI
Design and implementation of differential cascode voltage switch with pass-gate (DCVSPG) logic for high-performance digital systems
Fang-shi Lai,Wei Hwang +1 more
TL;DR: In comparison with other existing dynamic circuit techniques, the results also clearly show that the dynamic DCVSPG has the superior power-delay performance.