Proceedings ArticleDOI
Design of a Moore finite state machine using a novel reversible logic gate, decoder and synchronous up-counter
Matthew Morrison,Nagarajan Ranganathan +1 more
- pp 1445-1449
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TLDR
A reduced reversible implementation of a JK Flip Flop is implemented in a reduced reversible synchronous up-down counter, and this decoder and counter are then utilized in the design of a reversible Moore finite state machine.Abstract:
Reversible logic is an emerging nanotechnology widely being considered as the potential logic design and implementation of nanotechnology and quantum computing with the main goal of reducing physical entropy gain. Recent advances in reversible logic allow for new avenues in the implementation of reversible combinational circuits. Part of this advancement is the design and implementation of a finite state machine. A proposed novel 4*4 RD gate implemented as a 2-to-4 decoder with low delay and cost is presented, and a novel 4*4 R2D gate used in the implementation of a novel n-to-2n decoder with low cost and delay. A reversible synchronous up-down counter is presented and verified, and a reduced reversible implementation of a JK Flip Flop is implemented in a reduced reversible synchronous up-down counter. This decoder and counter are then utilized in the design of a reversible Moore finite state machine.read more
Citations
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Proceedings ArticleDOI
Design of static and dynamic RAM arrays using a novel reversible logic gate and decoder
TL;DR: A novel 4*4 MLMR gate is presented which is used for controlling the read/write logic of a SRAM cell and its implementation in a synchronous n-bit reversible dual-port SRAM array is shown.
Journal ArticleDOI
RMDDS: Reed-muller decision diagram synthesis of reversible logic circuits
Chia-Chun Lin,Niraj K. Jha +1 more
TL;DR: A flexible and efficient reversible logic synthesizer that exploits the complementary advantages of two methods: Reed-Muller Reversible Logic Synthesis and Decision Diagram Synthesis, and is thus called RMDDS.
Proceedings ArticleDOI
Design of a novel reversible ALU using an enhanced carry look- ahead adder
TL;DR: A novel programmable reversible logic gate is presented and verified, and its implementation in the design of a reversible Arithmetic Logic Unit is demonstrated.
Proceedings ArticleDOI
Design of a Tree-Based Comparator and Memory Unit Based on a Novel Reversible Logic Structure
TL;DR: A 2*2 Swap gate which is a reduced implementation in terms of quantum cost and delay to the previous Swap gate is presented and its advantages over the Toffoli and Peres gates are discussed.
Journal Article
Design, Optimization and Synthesis of Efficient Reversible Logic Binary Decoder
TL;DR: A Reversible low power Decoder is proposed, newly proposed decoder compared with already proposed reversible decoder and the Conventional decoder, and an algorithm for NX2 decoder is given.
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