Design of parity preserving reversible sequential circuits

TLDR: The proposed circuit designs are superior to the existing designs in terms of number of gates, garbage outputs and quantum costs and the proposed designs are fault tolerant.

Abstract: Irreversible computing requires consumption of energy to obtain missing bits due to overlapped mapping between input and output vectors. For this reason, reversible computing has become one of the most significant computing processes for the forthcoming computing technology as they dissipate very low power. Therefore, a major research objective in this field is the synthesis of different types of reversible latches and flip flops. A parity preserving reversible new gate is proposed in this paper. A modification of existing Peres gate is also proposed. Using the proposed gates, the conventional flip flops — RS flip flop, JK flip flop, D flip flop and T flip flop are designed. Therefore, the proposed designs are fault tolerant. The master-slave JK flip flop and master-slave D flip flop are also designed using the proposed gates. The proposed circuit designs are superior to the existing designs in terms of number of gates, garbage outputs and quantum costs.