scispace - formally typeset
Proceedings ArticleDOI

Design & simulation of successive approximation analog to digital converter using asynchronous control logic

TLDR
This work proposed asynchronous control logic technique to design low power, A/D converter that can be used for biomedical applications and does not employ any component trimming or adjustment.
Abstract
Analog to Digital converters (ADC) are main design blocks for high efficiency medical applications. This paper represents a low power SAR ADC that uses a monotonic switching procedure in which switching occurs in one direction only thus switching energy reduces. As compared to conventional converter capacitance is reduced and Common mode voltage is also suppressed in the proposed method. So, dynamic latch comparator is being used to reduce the offset caused due to variation in the common mode voltage. A reliable low-distortion CMOS bootstrapped sampling switch is used. This work proposed asynchronous control logic technique to design low power, A/D converter that can be used for biomedical applications and does not employ any component trimming or adjustment. We achieved 1mW power dissipation for the proposed circuit. This architecture is simulated at 180nm technology using Cadence tool at 1.8Vsupply voltage.

read more

References
More filters
Journal ArticleDOI

A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure

TL;DR: In this paper, a low-power 10-bit 50-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that uses a monotonic capacitor switching procedure is presented.
Proceedings ArticleDOI

An energy-efficient charge recycling approach for a SAR converter with capacitive DAC

TL;DR: A new method for switching the capacitors in the DAC capacitor array of a successive approximation register (SAR) ADC can be reduced by 37% compared to a conventional switching method by splitting the MSB capacitor into b - 1 binary scaled sub-capacitors.
Proceedings ArticleDOI

Split capacitor DAC mismatch calibration in successive approximation ADC

TL;DR: A split capacitor DAC calibration method is proposed that a bridge capacitor larger than conventional design allows a tunable capacitor to compensate for mismatch and a comparator with digital timing control offset cancellation is proposed.
Journal ArticleDOI

A 12 bit 160 MS/s Two-Step SAR ADC With Background Bit-Weight Calibration Using a Time-Domain Proximity Detector

TL;DR: A background bit-weight calibration exploiting the comparator resolving time information and the employment of a sub-binary DAC in the first SAR stage are two key techniques in this work to attain high conversion throughput and power savings at the same time using a simple, low-gain residue amplifier.