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Open AccessProceedings ArticleDOI

DR.SGX: automated and adjustable side-channel protection for SGX using data location randomization

TLDR
A compiler-based tool called DR.SGX is designed and implemented that instruments the enclave code, permuting data locations at fine granularity and periodically re-randomize all enclave data to break the link between the memory observations by the adversary and the actual data accesses by the victim.
Abstract
Recent research has demonstrated that Intel's SGX is vulnerable to software-based side-channel attacks. In a common attack, the adversary monitors CPU caches to infer secret-dependent data accesses patterns. Known defenses have major limitations, as they require either error-prone developer assistance, incur extremely high runtime overhead, or prevent only specific attacks. In this paper, we propose data location randomization as a novel defense against side-channel attacks that target data access patterns. Our goal is to break the link between the memory observations by the adversary and the actual data accesses by the victim. We design and implement a compiler-based tool called DR.SGX that instruments the enclave code, permuting data locations at fine granularity. To prevent correlation of repeated memory accesses we periodically re-randomize all enclave data. Our solution requires no developer assistance and strikes the balance between side-channel protection and performance based on an adjustable security parameter.

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Citations
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ReportDOI

Design Choices for Central Bank Digital Currency: Policy and Technical Considerations

TL;DR: This paper enumerates the fundamental technical design challenges facing CBDC designers, with a particular focus on performance, privacy, and security, and presents a vision of the rich range of functionalities and use cases that a well-designed CBDC platform could ultimately offer users.
Journal ArticleDOI

On the Convergence of Artificial Intelligence and Distributed Ledger Technology: A Scoping Review and Future Research Agenda

TL;DR: This research reviews and synthesizes extant research on integrating AI with DLT and vice versa to rigorously develop a future research agenda on the convergence of both technologies, and identifies research opportunities in the areas of secure DLT, automated referee and governance, and privacy-preserving personalization.
Posted Content

CURE: A Security Architecture with CUstomizable and Resilient Enclaves

TL;DR: CURE is proposed, the first security architecture, which tackles design challenges by providing different types of enclaves, and enables the exclusive assignment of system resources, e.g., peripherals, CPU cores, or cache resources to single enclaves.
Proceedings Article

V0LTpwn: Attacking x86 Processor Integrity from Software

TL;DR: V0LTpwn is a novel hardware-oriented but software-controlled attack that affects the integrity of computation in virtually any execution mode on modern x86 processors, and represents the first attack on x86 integrity from software.
Journal ArticleDOI

Security Vulnerabilities of SGX and Countermeasures: A Survey

TL;DR: Wang et al. as discussed by the authors proposed two sets of criteria for estimating security risks of existing attacks and evaluating defense effects brought by attack countermeasures, and proposed a taxonomy of SGX security vulnerabilities and shed light on corresponding attack vectors.
References
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Journal ArticleDOI

Software protection and simulation on oblivious RAMs

TL;DR: This paper shows how to do an on-line simulation of an arbitrary RAM by a probabilistic oblivious RAM with a polylogaithmic slowdown in the running time, and shows that a logarithmic slowdown is a lower bound.
Proceedings ArticleDOI

Spectre Attacks: Exploiting Speculative Execution

TL;DR: Spectre as mentioned in this paper is a side channel attack that can leak the victim's confidential information via side channel to the adversary. And it can read arbitrary memory from a victim's process.
Posted Content

Cache attacks and Countermeasures: the Case of AES.

TL;DR: In this article, the authors describe side-channel attacks based on inter-process leakage through the state of the CPU's memory cache, which can be used for cryptanalysis of cryptographic primitives that employ data-dependent table lookups.
Book ChapterDOI

Cache attacks and countermeasures: the case of AES

TL;DR: In this article, the authors describe side-channel attacks based on inter-process leakage through the state of the CPU's memory cache, which can be used for cryptanalysis of cryptographic primitives that employ data-dependent table lookups.
Posted Content

Intel SGX Explained.

TL;DR: In this article, the authors present a detailed and structured presentation of the publicly available information on SGX, a series of intelligent guesses about some important but undocumented aspects of SGX.
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Our solution requires no developer assistance and strikes the balance between side-channel protection and performance based on an adjustable security parameter.