Patent
Electrostatic discharge protection circuit for integrated circuits
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TLDR
In this article, an ESD protection circuit that uses the well-known SCR latchup effect present in CMOS processes to divert the ESD current pulse away from sensitive circuit structures is presented.Abstract:
An ESD protection circuit that uses the well-known SCR latchup effect present in CMOS processes to divert the ESD current pulse away from sensitive circuit structures. The circuit uses an inverter trigger device, with a voltage divider on its output, to control the amount of voltage necessary to cause latchup. This feature enables the SCR to absorb a high current pulse on the CMOS pad structures caused by an ESD event, while also preventing the circuit from latching when an ordinary CMOS voltage is applied to the pad while the circuit being protected is unpowered. The circuit insures that the SCR will latch independent of breakdown effects, while also allowing the threshold voltage at which latchup occurs to be adjusted into the circuit by varying the sizes of two FETS used as the voltage divider.read more
Citations
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Electrostatic discharge protection structures for high speed technologies with mixed and ultra-low voltage supplies
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References
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Journal ArticleDOI
A low-voltage triggering SCR for on-chip ESD protection at output and input pads
Amitava Chatterjee,T. Polgreen +1 more
TL;DR: In this article, a novel silicon-controlled rectifier (SCR) structure for on-chip protection against electrostatic discharge (ESD) stress at output or input pads is presented, which switches to an ON state at a trigger voltage determined by the gate length of an incorporated nMOS-like structure.
Patent
Integrated circuit protection device
TL;DR: In this article, a PNPN structure consisting of a silicon controlled rectifier (SCR) and metal-oxide-semiconductor (MOS) transistor integral to the SCR structure is used to protect circuitry formed within an integrated circuit from damage due to excessively high voltage transients.
Proceedings ArticleDOI
ESD on CHMOS Devices - Equivalent Circuits, Physical Models and Failure Mechanisms
TL;DR: In this paper, the location of energy dissipation during an EOS/ESD event is determined by a pulsed near infrared technique, and rules for predicting location of ESD dissipation are defined.
Proceedings ArticleDOI
ESD Phenomena and Protection Issues in CMOS Output Buffers
TL;DR: In this paper, the p-channel device of the buffer can be made to play a significant role and that this feature can be used to achieve good protection for positive stress with respect to both VDD and VSS.
Patent
Capacitively induced electrostatic discharge protection circuit
TL;DR: In this paper, an integrated circuit electrostatic discharge (ESD) protection circuit employs a capacitor and a zener diode to trigger a thick oxide ESD shunt field effect transistor (FET).