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Exploitation of Fine-Grain Parallelism
TLDR
This paper presents a meta-analysis of VLIW architectures for exploitation of fine-grain parallelism and describes the architecture and methods used for instruction scheduling.Abstract:
Kinds of parallelism.- Architectures for fine-grain parallelism.- VLIW machines.- Constraints on VLIW architectures.- Architectural support for exploitation of fine-grain parallelism.- Constraints for instruction scheduling.- Instruction-scheduling methods.- Developing instruction-scheduling methods.- Tools for instruction scheduling.- The machine model.- The horizontal instruction-scheduler.- Resource management.- Exceptions.- Vertical instruction-scheduling.- Conclusion.read more
Citations
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Journal ArticleDOI
Data Dependence Analysis of Assembly Code
TL;DR: In this article, a new approach for data dependence analysis on assembly language code is presented, which is based on symbolic value propagation and can derive value-based dependences between memory operations instead of just address-based dependencies.
Proceedings ArticleDOI
Data dependence analysis of assembly code
TL;DR: A new approach for determination of data dependences in assembly code is described, based on a sophisticated algorithm for symbolic value propagation, and it can derive value- based dependences between memory operations instead of address-based dependences, only.
Proceedings ArticleDOI
Compiling multimedia applications on VLIW architecture
TL;DR: A new compiler-directed approach to obtaining high-performance for multimedia applications by integrating high-level program restructuring and low-level scheduling is described.
Book ChapterDOI
A Multithreaded Implementation Concept of Prolog on Datarol-II Machine
Péter Kacsuk,Makoto Amamiya +1 more
TL;DR: The paper presents a massively parallel implementation method of Prolog on the multithreaded parallel machine, Datarol-II, which efficiently supports both the management of macrothreads derived from Logicflow Model and management of microthreads created when remote loads are necessary.
Proceedings ArticleDOI
Tuning the GNU instruction scheduler to superscalar microprocessors
A. Unger,Eberhard Zehendner +1 more
TL;DR: The circumstances that led to poorly scheduled code are analyzed and how the machine description supplied for a superscalar processor can be modified to fit some of these problems without hampering the portability of the GCC is demonstrated.