Proceedings ArticleDOI
Fast algorithms for static compaction of sequential circuit test vectors
M.S. Nsiao,E.M. Rudnick,J.H. Patel +2 more
- pp 188-195
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TLDR
Two fast algorithms for static test sequence compaction are proposed for sequential circuits, based on the observation that test sequences traverse through a small set of states, and some states are frequently re-visited throughout the application of a test set.Abstract:
Two fast algorithms for static test sequence compaction are proposed for sequential circuits. The algorithms are based on the observation that test sequences traverse through a small set of states, and some states are frequently re-visited throughout the application of a test set. Subsequences that start and end on the same states may be removed if necessary and sufficient conditions are met for them. The techniques require only two fault simulation passes and are applied to test sequences generated by various test generators, resulting in significant compactions very quickly for circuits that have many revisited states.read more
Citations
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Proceedings ArticleDOI
Vector restoration based static compaction of test sequences for synchronous sequential circuits
Irith Pomeranz,Sudhakar M. Reddy +1 more
TL;DR: A new procedure for static compaction that belongs to the class of procedures that omit test vectors from a given test sequence in order to reduce its size without reducing the fault coverage, and then restores some of them as necessary to achieve the required fault coverage.
Proceedings ArticleDOI
State relaxation based subsequence removal for fast static compaction in sequential circuits
Michael S. Hsiao,S.T. Chakradhar +1 more
TL;DR: The subsequence removal technique is extended to provide significantly higher static compaction for sequential circuits and it is shown that state relaxation techniques can be used to identify more or larger cycles in a test set.
Proceedings ArticleDOI
Procedures for static compaction of test sequences for synchronous sequential circuits based on vector restoration
TL;DR: Several compaction procedures for synchronous sequential circuits based on test vector restoration are proposed, including limiting the test vectors initially omitted from the test sequence, consideration of several faults in parallel during restoration, and the use of a parallel fault simulator.
Proceedings ArticleDOI
Static compaction using overlapped restoration and segment pruning
TL;DR: A new technique for static compaction of test sequences based on overlapped vector restoration and identification, pruning, and re-ordering of segments was able to successfully process large industrial designs that could not be handled by earlier techniques in 2 CPU days.
Journal ArticleDOI
Efficient techniques for dynamic test sequence compaction
TL;DR: Significant improvements in test set size, fault coverage, and test generation time have been obtained over previous approaches using combinations of the three techniques.
References
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Book
Introduction to Algorithms
TL;DR: The updated new edition of the classic Introduction to Algorithms is intended primarily for use in undergraduate or graduate courses in algorithms or data structures and presents a rich variety of algorithms and covers them in considerable depth while making their design and analysis accessible to all levels of readers.
Journal ArticleDOI
Introduction to algorithms: 4. Turtle graphics
TL;DR: In this article, a language similar to logo is used to draw geometric pictures using this language and programs are developed to draw geometrical pictures using it, which is similar to the one we use in this paper.
Proceedings ArticleDOI
Combinational profiles of sequential benchmark circuits
F. Brglez,D. Bryan,K. Kozminski +2 more
TL;DR: A set of 31 digital sequential circuits described at the gate level that extend the size and complexity of the ISCAS'85 set of combinational circuits and can serve as benchmarks for researchers interested in sequential test generation, scan-basedtest generation, and mixed sequential/scan-based test generation using partial scan techniques.
Proceedings ArticleDOI
HITEC: a test generation package for sequential circuits
TL;DR: HITEC is presented, a sequential circuit test generation package to generate test patterns for sequential circuits, without assuming the use of scan techniques or a reset state, and several new techniques are introduced to improve the performance of test generation.
Proceedings ArticleDOI
Sequential Circuit Test Generation in a Genetic Algorithm Framework
TL;DR: A genetic algorithm (GA) framework for sequential circuit test generation that evolves candidate test vectors and sequences, using a fault simulator to compute the fitness of each candidate test.
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