Fault-based automatic test generator for linear analog circuits
Naveena Nagi,Abhijit Chatterjee,Ashok Balivada,Jacob A. Abraham +3 more
- pp 88-91
TLDR
This simulation-assisted technique automatically determines the test frequencies to detect AC faults in linear analog circuits with the help of hierarchical fault models for parametric and catastrophic faults and a very efficient fault simulator.Abstract:
Recognizing that specification testing of analog circuits involves a high cost and lacks any quantitative measure of the testing process, we adopt a fault-based technique. With the help of hierarchical fault models for parametric and catastrophic faults, and a very efficient fault simulator, our simulation-assisted technique automatically determines the test frequencies to detect AC faults in linear analog circuits. By a suitable choice of parameters in the test generator, we can either determine the best test (maximize the error between the good and the faulty responses) for every fault (resulting in a large test set), or generate the smallest test set for all the faults. Finally, fault coverage values provide a quantitative evaluation of the final test set.read more
Citations
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Prediction of analog performance parameters using fast transient testing
TL;DR: A fast transient testing methodology for predicting the performance parameters of analog circuits showed a ten times speedup in production testing; accurate prediction of the performance parameter; and a simpler test configuration.
Proceedings ArticleDOI
Enhancing test effectiveness for analog circuits using synthesized measurements
P.N. Variyam,Abhijit Chatterjee +1 more
TL;DR: This paper addresses the critical issue of accurate test threshold determination for these alternate tests by proposing to post-process the given set of sensitive and linearly independent measurements to synthesize a new set of measurements based on which the pass/fail decision is made.
Journal ArticleDOI
Pseudorandom testing for mixed-signal circuits
Chen-Yang Pan,Kwang-Ting Cheng +1 more
TL;DR: A universal input stimulus (white noise) is used and thus test generation can be avoided, signatures for high quality testing can be easily constructed and thus testing cost can be minimized, and the scheme can be used for Built-In Self-Test (BIST) implementation for DSP-based mixed-signal designs.
Proceedings ArticleDOI
Analytical fault modeling and static test generation for analog ICs
Giri Devarayanadurg,Mani Soma +1 more
TL;DR: Using the technique presented here an efficient static test set for analog and mixed-signal ICs can be constructed, reducing both the test time and the packaging cost.
Journal ArticleDOI
Multifrequency analysis of faults in analog circuits
M. Slamani,Bozena Kaminska +1 more
TL;DR: The authors use the same test methodology to analyze all three fault types, and their algorithm indicates the set of adequate test frequencies and nodes that increase fault observability.
References
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An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
TL;DR: PODEM (path-oriented decision making) is a new test generation algorithm for combinational logic circuits that uses an implicit enumeration approach analogous to that used for solving 0-1 integer programming problems and is significantly more efficient than DALG over the general spectrum of combinational Logic circuits.
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Analog filter design
TL;DR: In this paper, Bilinear Transfer Functions and Frequency Response are discussed in the context of Op-Amp Oscillators, and a ladder design with simulated elements is presented.
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Detection of catastrophic faults in analog integrated circuits
L. Milor,V. Visvanathan +1 more
TL;DR: The construction of a set of measurements that detects many faulty circuits before specification testing is described, and its effectiveness in detecting faulty circuits is evaluated.
Proceedings ArticleDOI
A design-for-test methodology for active analog filters
TL;DR: A DFT (design-for-test) methodology to improve the controllability/observability of internal signals in active filters is presented, which is suitable for silicon compiler and CAD (computer-aided-design) implementation.
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