Proceedings ArticleDOI
FPGA implementation of efficient FIR Filter with quantized fixedpoint coefficients
Santosh Bhalke,B. M. Manjula,Chirag Sharma +2 more
- pp 1-6
TLDR
In this paper the design of digital FIR filter using Finite State Machine (FSM) is implemented, and the filter coefficients used are fixed-point coefficients, which will reduce the truncation and computation complexity.Abstract:
Finite Impulse Response (FIR) Filters is a digital filter which is used in digital signal processing like communicate-on, biomedical signal processing, image processing, etc. These Digital filters are used to filter out the part of signal that is redundant or damages the original signal. In this paper we have implemented a design of digital FIR filter using Finite State Machine (FSM). In this approach it is possible to reuse the hardware implemented so that the area will be reduced significantly, and also the delay and power will be reduces as compared to the MATLAB - Simulink based FIR Filters. In this design the filter coefficients used are fixed-point coefficients, which will reduce the truncation and computation complexity.read more
Citations
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Book ChapterDOI
Artificial Intelligence-Based Load Balancing in Cloud Computing Environment: A Study
TL;DR: This paper presents the design of 4-tap and 8-bit fast low-pass FIR filter design under FPGA background using hardware description language (HDL) to improve integration, increment work speed and framework abilities.
Book ChapterDOI
Field Programmable Gate Array (FPGA)-Based Fast and Low-Pass Finite Impulse Response (FIR) Filter
R. Raja Sudharsan,J. Deny +1 more
TL;DR: In this article, a 4-tap and 8-bit fast low-pass FIR filter design under FPGA background using hardware description language (HDL) is presented, where the main attention of this FIR filter is focused towards the noise and performance constraints.
Proceedings ArticleDOI
Synthesis of FIR Filter using ADC-DAC: A FPGA Implementation
TL;DR: 8 bit and 8 taps FIR filter for filtering of Noise level and band pass filter for stabilizing the frequency and results in optimization of noise by 13% comparing to the internal noise from analog signal.
Proceedings ArticleDOI
Design of FIR Filter using reconfigurable MAC unit
Deepika,Nidhi Goel +1 more
TL;DR: In this paper FIR filter has been designed by using a reconfigurable Booth multiplier and a Carry Look Ahead Adder to make FIR filter faster.
Journal ArticleDOI
A Power-Efficient Multichannel Low-Pass Filter Based on the Cascaded Multiple Accumulate Finite Impulse Response (CMFIR) Structure for Digital Image Processing
Vivek Jain,Prasun Chakrabarti,Massimo Mitolo,Zbigniew Leonowicz,Michal Jasinski,Alexander Vinogradov,Vadim Bolshev +6 more
TL;DR: In this article , the authors proposed a power-efficient multichannel low-pass filter for digital image processing based on the cascade multiple accumulate finite impulse response (CMFIR) structure.
References
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Book
Circuit Design with VHDL
TL;DR: This book's highly original approach of teaching through extensive system examples as well as its unique integration of VHDL and design make it suitable both for use by students in computer science and electrical engineering.
Book
A VHDL primer
TL;DR: VHDL-93 features,Packages and Libraries, Generics and Configurations, Subprograms and Subprogram Overloading, and More on Ports.
Book
FSM-based Digital Design using Verilog HDL
Peter Minns,Ian Elliott +1 more
TL;DR: This clear and logical book presents a range of novel techniques for the rapid and reliable design of digital systems using FSMs, detailing exactly how and where they can be implemented.
Journal ArticleDOI
Design of linear-phase direct-form FIR digital filters with quantized coefficients using error spectrum shaping
TL;DR: It is shown that the expected disturbance filter frequency response due to quantization can be controlled and the effect is concentrated in tolerant frequency bands and significantly reduced in critical ones.
Performance Analysis of High Speed Low Power Carry Look-Ahead Adder Using Different Logic Styles
Jagannath Samanta,Mousam Halder +1 more
TL;DR: In this paper a 4 bit & 8 bit CLA has been implemented using different static and dynamic logic styles such as Standard CMOS, DCVS Pseudo NMOS, PTL & Domino logic style.