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Proceedings ArticleDOI

HABIST: histogram-based analog built in self test

A. Frisch, +1 more
- pp 760-767
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TLDR
The HABIST method and optional variations in its implementation, algorithms for processing histograms to obtain signatures and other compressed form of data, including waveform parameters, examples of the difference histograms that result from applying the algorithm, and methods and circuits for histogram generation are described.
Abstract
This histogram based method of test collects a statistical representation of the activity at a node and processes that representation using a template histogram as a reference. In most cases, no special stimulus is required-data is collected in-situ, while the circuit under test is functioning. (Alternatively, analog stimulus, e.g. using a pseudo random sequence generator or stored digital vectors with a D to A converter, may be provided). The result of processing the data against the template histogram is a compressed human readable signature that defines gain, offset, noise, and distortion errors. These errors can then be used heuristically to determine causation. This paper describes the HABIST method and optional variations in its implementation, algorithms for processing histograms to obtain signatures and other compressed form of data, including waveform parameters, examples of the difference histograms that result from applying the algorithm, and methods and circuits for histogram generation.

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Citations
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Proceedings ArticleDOI

Hardware resource minimization for histogram-based ADC BIST

TL;DR: The paper proposes a BIST approach for deriving the main characterization parameters of ADCs from histogram data and Pseudo-algorithms are given to derive offset, gain error and nonlinearities.
Journal ArticleDOI

A Low-Cost BIST Architecture for Linear Histogram Testing of ADCs

TL;DR: This paper investigates the viability of an ADC BIST scheme for implementing the histogram test technique and shows that the choice of a triangle-wave input signal combined with an appropriate time decomposition technique of the test procedure permits to drastically reduce the required on-chip hardware circuitry.
Proceedings ArticleDOI

An ADC-BiST scheme using sequential code analysis

TL;DR: This paper presents a built-in self-test (BiST) scheme for analog to digital converters (ADC) based on a linear ramp generator and efficient output analysis and presents two implementation options based on how much on-chip resources are available.
Journal ArticleDOI

Digital-compatible BIST for analog circuits using transient response sampling

TL;DR: The BIST scheme presented here maximizes coverage of parametric and catastrophic failures and provides an all-digital BIST solution to analog circuits.
Proceedings ArticleDOI

An ADC-BiST Scheme Using Sequential Code Analysis

Erdogan, +1 more
References
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Proceedings ArticleDOI

A BIST scheme for an SNR test of a sigma-delta ADC

TL;DR: The MAD-BIST strategy for the SNR test of the A/D converter is introduced, accuracy issues are discussed, and experimental results are presented.
Patent

Method and apparatus for providing a histogram

TL;DR: In this paper, a pseudo-random sequence in a shift register connected in a predetermined feedback relation is generated for a histogram element storage location in a random access memory and is used for loading the shift register in parallel when an event corresponding to that element takes place.
Patent

Digitizer effective resolution measurement system using sinewave parameter estimation

TL;DR: In this paper, a method and apparatus for determining the effective bits of resolution of a digitizer was proposed, wherein amplitude, frequency, phase angle and offset parameters characterizing a sinewave input signal to the digitizers were estimated from the waveform data sequence produced by the digizer in response to the input signal.
Proceedings ArticleDOI

Histogram-based distortion and gain tracking testing of an 8-bit PCM mixed analog-digital IC chip

TL;DR: The effective number of bits of a linear analog-to-digital converter (ADC) can be computed using the code density histogram method using a very simple model using additive white Gaussian noise.
Proceedings ArticleDOI

Supplying known good die for MCM applications using low cost embedded testing

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