Journal ArticleDOI
High-speed CMOS circuit technique
Jiren Yuan,Christer Svensson +1 more
TLDR
It is shown that clock frequencies in excess of 200 MHz are feasible in a 3- mu m CMOS process, and a precharge technique with a true single-phase clock, which increases the clock frequency and reduces the skew problems, is used.Abstract:
It is shown that clock frequencies in excess of 200 MHz are feasible in a 3- mu m CMOS process. This performance can be obtained by means of clocking strategy, device sizing, and logic style selection. A precharge technique with a true single-phase clock, which increases the clock frequency and reduces the skew problems, is used. Device sizing with the help of an optimizing program improves circuit speed by a factor of 1.5-1.8. The logic depth is minimized to one instead of two or more, and pipeline structures are used wherever possible. Experimental results for several circuits which work at clock frequencies of 200-230 MHz are presented. SPICE simulation shows that some circuits could work up to 400-500 MHz. >read more
Citations
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Journal ArticleDOI
Minimizing power consumption in digital CMOS circuits
TL;DR: An approach is presented for minimizing power consumption for digital systems implemented in CMOS which involves optimization at all levels of the design and has been applied to the design of a chipset for a portable multimedia terminal that supports pen input, speech I/O and full-motion video.
Journal ArticleDOI
Self-powered signal processing using vibration-based power generation
TL;DR: In this paper, the authors demonstrate the feasibility of operating a digital system from power generated by vibrations in its environment, using a moving coil electromagnetic transducer as a power generator.
Journal ArticleDOI
A 200-MHz 64-b dual-issue CMOS microprocessor
Daniel W. Dobberpuhl,R. Witek,R. Allmon,R. Anglin,D. Bertucci,S.M. Britton,L. Chao,R.A. Conrad,D.E. Dever,B. Gieseke,Soha Hassoun,G. Hoeppner,K. Kuchler,M. Ladd,B.M. Leary,L. Madden,Edward J. McLellan,D.R. Meyer,J. Montanaro,Donald A. Priore,V. Rajagopalan,S. Samudrala,S. Santhanam +22 more
TL;DR: A RISC (reduced-instruction-set computer)-style microprocessor operating up to 200 MHz, implements a 64-b architecture that provides huge linear address space without bottlenecks that would impede highly concurrent implementations.
Journal ArticleDOI
Intra-chip wireless interconnect for clock distribution implemented with integrated antennas, receivers, and transmitters
Brian Floyd,Chih-Ming Hung +1 more
TL;DR: This is the first known demonstration of an on-chip clock transmitter with an integrated antenna and the second demonstration of a clock receiver with anIntegrated antenna, where the receiver's frequency and interconnection distance have approximately been doubled over previous results.
Journal ArticleDOI
Trading speed for low power by choice of supply and threshold voltages
Dake Liu,Christer Svensson +1 more
TL;DR: In this article, the tradeoff between speed and power consumption for low power consumption in CMOS VLSI by using the supply voltage and the threshold voltage as variables was investigated.
References
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Journal ArticleDOI
A true single-phase-clock dynamic CMOS circuit technique
TL;DR: The authors describe two dynamic circuit techniques, using only a single-phase clock which is never inverted, which has the advantages of simple clock distribution, small area for clock lines reduced clock skew problems, and high speed.