Patent
Inverse T-gate semiconductor device with self-aligned punchthrough stops and method of fabrication
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TLDR
In this article, an inverse T gate comprising an upper member and a lower member is formed on a well of a first conductivity type, and a gate insulating layer is formed between the composite gate and the well.Abstract:
A high speed submicron metal-oxide-semiconductor transistor which exhibits a high immunity to hot electron degradation, good performance, and excellent punchthrough characteristics. An inverse T gate comprising an upper member and a lower member is formed on a well of a first conductivity type. A gate insulating layer is formed between the composite gate and the well. A pair of first conductivity type punchthrough stop regions are formed apart in the well in alignment with the laterally opposite sides of the upper gate member. A first oxide sidewall spacer is formed adjacent to laterally opposite sidewalls of the upper gate member on the lower gate member. A first pair of source/drain regions of a second conductivity type are formed in alignment with the first oxide sidewall spacers. A second sidewall spacer is formed adjacent to each of the first sidewall spacers on the lower gate member. A second source and second drain region of the second conductivity type are formed in the first source and first drain regions, respectively. The second source and second drain regions are formed in alignment with the outer edges of the second sidewall spacers.read more
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References
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Patent
Self-aligned overlap MOSFET and method of fabrication
TL;DR: In this paper, a high speed submicron transistor which exhibits a high immunity to hot electron degradation and is viable for VLSI manufacturing is presented, where an inner gate member is formed on a p type substrate.
Journal ArticleDOI
Drain-engineered hot-electron-resistant device structures: a review
TL;DR: In this paper, the authors provide guidelines for the fabrication of hot-electron-resistant device structures and make suggestions with reference to device structures suitable for a manufacturing environment, and provide a detailed review of various MOS structures with specially designed drain regions.
Patent
Metal oxide semiconductor field effect transistor and method of making the same
TL;DR: In this paper, a MOSFET comprising a substrate of a first conductivity type, a gate located on the substrate, a channel region of the first conductivities type located beneath a surface portion of the substrate corresponding to a region defined beneath said gate, low concentration and high concentration source regions of a second conductivities types located beneath the surface of a substrate, and low-concentration drain regions of the second conductivity types located at opposite sides of the channel region.
Proceedings ArticleDOI
A novel submicron LDD transistor with inverse-T gate structure
TL;DR: In this article, a novel inverse-T LDD (ITLDD) transistor is proposed, which features self alignments of n-LDD and n+source-drain implants to the inside and outside edge, respectively, of the IT gate structure.
Patent
Submicron lightly doped field effect transistors
TL;DR: In this article, a lightly doped field effect transistor has a central gate portion and source and drain portions spaced to opposite sides thereof and each having a heavily doped contact section and a sidewall spacer portion between the gate and contact section.