Patent
Iterative method for establishing connections and resulting product
Reads0
Chats0
TLDR
In this article, a method for establishing connections by automatically routing a plurality of paths between individual components using initially simple connection path shapes is proposed, which is used to create an interconnection package with better use of wiring space.Abstract:
A method for establishing connections by automatically routing a plurality of paths between individual components using initially simple connection path shapes. The method is used to create an interconnection package with better use of wiring space. Each connection, in turn, is removed if previously routed, rerouted and evaluated according to specified penalty costs to minimize undesirable routing characteristics. This method is particularly advantageous in providing automatic path routing in directionally uncommitted planes for wiring highly integrated electric circuits, or the like.read more
Citations
More filters
Patent
Advanced modular cell placement system
TL;DR: In this article, a system for determining an affinity associated with relocating a cell located on a surface of a semiconductor chip to a different location on the surface is described, where each cell may be part of a cell net containing multiple cells.
Patent
Metal layer assignment
TL;DR: In this paper, a routing description that includes connection segments and a vertex where at least two of the connection segments connect to each other is obtained, and a penalty is determined for the vertex based on a potential layer assignment combination for the connect segments that connect at the vertex, and routing layers are assigned to the connected segments based on the determined penalty.
Patent
Advanced modular cell placement system with overlap remover with minimal noise
TL;DR: In this article, a method for refining the position of linearly aligned cells on the surface of a semiconductor chip is presented, which consists of defining an array of spaces between cells based on maximum and minimum cell positions, establishing a minimum spacing between cells, and linearly shifting cells in a predetermined manner such that no cells are closer to one another than the minimum space between cells.
Patent
The use of redundant routes to increase the yield and reliability of a vlsi layout
TL;DR: In this article, a method and system for inserting redundant paths (40,50) into an integrated circuit is described, which provides a method for identifying a single via (30) in a first path connecting two elements, determining if an alternate route is available for connecting the two elements (10,20) (other than a redundant via (54)), and for inserting a second path (50)into the available alternate route (70).
Patent
Method for estimating routability and congestion in a cell placement for integrated circuit chip
TL;DR: In this article, a method for estimating routing density in the placement of a microelectronic integrated circuit includes superimposing a pattern of contiguous tiles over the placement, with each of the tiles having edges.
References
More filters
Journal ArticleDOI
An Algorithm for Path Connections and Its Applications
TL;DR: The algorithm described in this paper is the outcome of an endeavor to answer the following question: Is it possible to find procedures which would enable a computer to solve efficiently path-connection problems inherent in logical drawing, wiring diagramming, and optimal route finding?
Patent
Optimization of an organization of many discrete elements
TL;DR: In this article, the overall arrangement of a large number of discrete objects may be optimized with relation to the function of or the space occupied by the arrangement by establishing a suitability measure, or score, for each configuration of the arrangement, in relation to a function of the or volume occupied, generating random local changes in the arrangement.
Patent
Element placement system
TL;DR: In this article, a system for assigning a plurality of interrelated circuit elements to element positions in an array of element positions on a circuit board is described, which includes means for storing an indication of the interrelationship of the elements being assigned and the order in which the elements are to be assigned.
Patent
Input/output signal point assignment
D. Isett Donald,W. Lomax John +1 more
TL;DR: In this paper, active components such as logic gates or flip-flops formed in a semiconductor substrate are interconnected to input/output bonding pads and other active components in a circuit array in four separate operations.
Patent
Machine process for positioning interconnected components to minimize interconnecting line length
TL;DR: In this paper, a machine process is disclosed in which components of an interconnected network are simultaneously repositioned and their interconnections simultaneously reordered to minimize interconnecting line length.