Patent
Logic circuit and full adder using the same
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TLDR
In this paper, a logic circuit capable of suppressing occurrence of wraparound of signals, capable of reducing power consumption, and in addition achieving a reduction of a circuit scale and an improvement of an operating speed and a full adder using the same, is presented.Abstract:
A logic circuit capable of suppressing occurrence of wraparound of signals, capable of reducing power consumption, and in addition achieving a reduction of a circuit scale and an improvement of an operating speed and a full adder using the same, wherein provision is made of an exclusive-OR generation circuit 12 for receiving a first logic signal A and a second logic signal B taking a logic “1” or “0” and generating the exclusive-OR of the first logic signal A and the second logic signal B, a dual signal generation circuit 11 for receiving the first logic signal A and the second logic signal B and generating the dual signal of the exclusive-OR of the first logic signal A and the second logic signal B, and an interpolation circuit 13 for compulsorily setting the output level of the dual signal at the level of the logic “1” when the output level of the exclusive-OR is the logic “0”, while compulsorily setting the output level of the exclusive-OR at the level of the logic “0” when the output level of the dual signal is the logic “1”.read more
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References
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Patent
Transfer method of thin-film device, the thin-film device, thin-film integrated circuit device, active matrix substrate, liquid crystal display device, and electronic apparatus
TL;DR: In this article, the authors proposed a simple manufacturing process and a low-cost thin-film device, while laminating order at manufacturing of a thin-filament device is maintained, by allowing transfer of the thinfilm device to a substrate at actual use.
Journal ArticleDOI
A 64-bit carry look ahead adder using pass transistor BiCMOS gates
TL;DR: In this paper, a 64-bit two-stage carry look ahead adder utilizing pass transistor BiCMOS gate was described, which has a rail-to-rail output voltage.
Patent
Full adder circuit
TL;DR: A full adder that operates rapidly with low power supply voltage and minimal power consumption, and further, that occupies a small area on a semiconductor element is considered in this article.
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Three-to-two carry save adder cell
TL;DR: The three-to-two adder as mentioned in this paper takes advantage of the fact that one of the inputs lags behind the other two inputs and provides an output within two gate delays from the time that the last to arrive signal is valid.
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