Proceedings ArticleDOI
Low hardware overhead scan based 3-weight weighted random BIST
Seongrnoon Wang
- pp 868-877
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TLDR
Experimental results show that the proposed BIST schemes can attain 100% fault coverage for all of benchmark circuits with drastically reduced test sequence lengths, achieved at low hardware cost even for benchmark circuits that have large number scan inputs.Abstract:
Two noble scan based BIST architectures, namely parallel fixing and serial fixing BIST, which can be implemented at very low hardware cost even for random pattern resistant circuits that have large number of scan elements, are proposed. Both of the proposed BIST schemes use 3-weight weighted random BIST techniques to reduce test sequence lengths by improving detection probabilities of random pattern resistant faults. A special ATPG is used to generate suitable test cube sets that lead to BIST circuits that require minimum hardware overhead. Experimental results show that the proposed BIST schemes can attain 100% fault coverage for all of benchmark circuits with drastically reduced test sequence lengths. This reduction in test sequence length is achieved at low hardware cost even for benchmark circuits that have large number scan inputs.read more
Citations
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Journal ArticleDOI
Test set embedding for deterministic BIST using a reconfigurable interconnection network
Lei Li,Krishnendu Chakrabarty +1 more
TL;DR: A reconfigurable interconnection network (RIN) is placed between the outputs of a pseudorandom pattern generator and the scan inputs of the circuit under test (CUT) to reduce correlation between the test data bits that are fed into the scan chains.
Proceedings ArticleDOI
Generation of low power dissipation and high fault coverage patterns for scan-based BIST
TL;DR: A low hardware overhead test pattern generator (TPG) for scan-based BIST that can reduce switching activity in CUTs during BIST and also achieve very high fault coverage with a reasonable length of test sequence is presented.
Proceedings ArticleDOI
Using embedded FPGAs for SoC yield improvement
TL;DR: It is shown how an FPGA core can provide embedded testers for other cores in the SoC, so that cores designed to be testing with external vectors can be tested with BIST, and the entire SoC can be tests with a low-cost tester.
Journal ArticleDOI
A BIST TPG for Low Power Dissipation and High Fault Coverage
TL;DR: Experimental results for ISCas'89 benchmark circuits demonstrate that the proposed BIST can significantly reduce switching activity during BIST while achieving 100% fault coverage for all ISCAS' 89 benchmark circuits.
Proceedings ArticleDOI
Hardware efficient LBIST with complementary weights
TL;DR: Experiments show that two complementary weights are sufficient for weighted random pattern testing and it presents a novel direction for exploiting weighted patterns.
References
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Book
Genetic algorithms in search, optimization, and machine learning
TL;DR: In this article, the authors present the computer techniques, mathematical tools, and research results that will enable both students and practitioners to apply genetic algorithms to problems in many fields, including computer programming and mathematics.
Genetic algorithms in search, optimization and machine learning
TL;DR: This book brings together the computer techniques, mathematical tools, and research results that will enable both students and practitioners to apply genetic algorithms to problems in many fields.
Journal Article
SIS : A System for Sequential Circuit Synthesis
TL;DR: This paper provides an overview of SIS and contains descriptions of the input specification, STG (state transition graph) manipulation, new logic optimization and verification algorithms, ASTG (asynchronous signal transition graph] manipulation, and synthesis for PGA’s (programmable gate arrays).
Journal ArticleDOI
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
TL;DR: PODEM (path-oriented decision making) is a new test generation algorithm for combinational logic circuits that uses an implicit enumeration approach analogous to that used for solving 0-1 integer programming problems and is significantly more efficient than DALG over the general spectrum of combinational Logic circuits.
Book
Built In Test for VLSI: Pseudorandom Techniques
TL;DR: Digital Testing and the Need for Testable design Principles of Testable Design Pseudorandom Sequence Generators Test Response Compression Techniques and Limitations and Other Concerns of Random Pattern Testing Test System Requirements for Built-In Test Appendix References Index.