Macropipelined multicomputer architecture for image analysis

TLDR: A scheme for macropipelining an L-stage image-analysis algorithm into a message-passing Ns-processor multicomputer system in which Ns > L is presented, believing that this scheme yields effective architectures for high-speed processing of long sequences of images.

Abstract: We present a scheme for macropipelining an L-stage image-analysis algorithm into a message-passing Ns-processor multicomputer system in which Ns > L. The resulting architectures achieve high speeds in processing multiple images. Most image-processing applications consist of a sequence of tasks, e.g., preprocessing, detection, segmentation, feature extraction, and classification. This sequence lends itself to an assignment of the tasks to a series-connected set of processors, or pipelining of the tasks. We refer to this form of pipelining as macropipelining. To minimize the effects of throughput-limiting tasks, or bottlenecks, in this pipeline, we introduce a performance model that accounts for both the computation aspects and the communication aspects of parallel processing. With the help of this model, we assign the appropriate number of processors to each task so as to balance the workloads. We then generate a problem graph describing the relationships among the tasks. We use an estimator of the frame-time of the image-processing system as an objective function for choosing a mapping of the problem processing graph into a system graph. This estimator takes account of computation times and communication intensities the tasks in the problem graph, and it accounts for link contentions. To find an efficient mapping, we use a among heuristic optimization in which possible bottlenecks are given high priority in the mapping procedure. We tested our macropipelining scheme on a target-recognition algorithm in a simulated hypercube computer system. The results support our belief that this scheme yields effective architectures for high-speed processing of long sequences of images.