scispace - formally typeset
Proceedings ArticleDOI

Measuring energy consumption in VLSI circuits: A foundation

Gloria Kissin
- pp 99-104
Reads0
Chats0
TLDR
Two energy models are developed, Model 1, the Uniswitch Model (USM), assumes that a wire or gate in an acyclic circuit can switch at most once, and Model 2, the Multiswitch model (MSM), is more sensitive to timing issues that can cause wires and gates in an acupuncture circuit to switch more than once.
Abstract
Energy conservation is a key question in today' s society and the proliferation of VLSI circuits encourages an energy conscious approach to their design. Although a single chip at current densities may consume less than one watt of power, assembling larger and larger systems with these chips results in significant energy costs [Me 80]. Moreover, energy consumed by a circuit is dissipated, typically by convection, as heat. The heat dissipated is proportional to the energy consumed. Increased densities in planar technologies and the possibility of 3-dimensional technologies, therefore, increase the need to reduce the amount of heal. produced. The intent of this paper is to lay the ground work for measuring the switching energy consumed in VLSI circuits. Intuitively, switching energy measures the area “used” to effect a computation. A wire or gate consumes switching energy when it changes staie from 0 to 1 or from 1 to 0. Some technologies consume more than switching energy. For example, nMOS dissipates DC power [MC 80]. CMOS, however, consumes only switching energy [MC 80]. Switching energy is thus a lower bound on total energy, and is alternately termed “energy” throughout this paper. In this paper, two energy models are developed, Model 1, the Uniswitch Model (USM), assumes that a wire or gate in an acyclic circuit can switch at most once. In particular, wire delays are neglected, the affects of different path lengths are neglected (ie. circuits are synchronous [Sa 76]), and all inputs are assumed to arrive together. Model 2, the Multiswitch Model (MSM), is more sensitive to timing issues that can cause wires and gates in an acyclic circuit to switch more than once. The rest of this paper is organized as follows. Section 2 defines the energy models. In section 3, a class of restricted acyclic circuits is defined. Lower and upper bounds for worst case energy are obtained for these circuits. An Ω(area) lower bound is obtained for acyclic monotone circuits. In section 4, average energy bounds are obtained for the restricted circuits.

read more

Citations
More filters
Journal ArticleDOI

Circuit activity based logic synthesis for low power reliable operations

TL;DR: A system developed to synthesize both finite state machines and combinational logic for low-power applications, called SYCLOP, is described, which tries to minimize the transition density at the internal nodes of a circuit to minimize power dissipation during normal operation.
Journal ArticleDOI

A mathematical basis for power-reduction in digital VLSI systems

TL;DR: A mathematical basis for power-reduction in VLSI systems is employed to derive lower bounds on the power dissipation in digital systems and unify existing power- reduction techniques under a common framework.
Proceedings ArticleDOI

Power-delay characteristics of CMOS multipliers

TL;DR: Simulation was used to establish a set of models for both delay and power dissipation, and those models were then used to compute the power-delay products of the multipliers.
Proceedings ArticleDOI

Estimating the power consumption of CMOS adders

TL;DR: Six types of adders are examined in an attempt to model their power dissipation and it is shown that the use of a relatively simple model provides results that are qualitatively accurate, when compared to more sophisticated models and to physical implementations of the circuits.
References
More filters
Book

Introduction to VLSI systems

Book

A complexity theory for VLSI

TL;DR: A "VLSI model of computation" is developed and upper and lower bounds on the silicon area and time required to solve the problems of sorting and discrete Fourier transformation are derived.
Journal ArticleDOI

On Relating Time and Space to Size and Depth

TL;DR: Turing machine space complexity is related to circuit depth complexity, which complements the known connection between Turing machine time and circuit size, thus enabling the related nature of some important open problems concerning Turing machine and circuit complexity to be exposed.
Journal ArticleDOI

The Area-Time Complexity of Binary Multiplication

TL;DR: By using a model of computation which is a realistic approx~mauon to current and anucipated LSI or VLSI technology, it is shown that A T 2.0 is shown to be the time required to perform multtphcaUon of n-bit binary numbers on a chip.