Method for forming dual gate oxides on integrated circuits with advanced logic devices

TLDR: In this article, a process for reducing the thickness of a native oxide film which is formed during the formation of MOSFET devices on a silicon wafer in a dual thickness gate oxide process is described.

Abstract: A process for significantly reducing the thickness of and improving the quality and uniformity of a native oxide film which is formed during the formation of MOSFET devices on a silicon wafer in a dual thickness gate oxide process. The native oxide forms on exposed silicon surfaces after selectively etching away regions of a first thicker gate oxide and prior to growing a thinner gate oxide. The thinner gate oxide used to form high performance devices is between about 15 and 50 Å thick. The native oxide which forms on the exposed silicon surfaces has an initial thickness of about 10 Å. After the selective regions have been patterned the wafer is cleaned using a totally HF free cleaning procedure and subjected to a low pressure rapid thermal annealing between about 600 and 1,050° C. in an ambient of H2 and N2. The residual oxide thickness is reduced to about 4 Å with an accompanying improvement in thickness uniformity and oxide quality. The residual film is more robust that the initial native oxide and forms a much smaller thickness component of the final thinner gate oxide. After the annealing treatment, the residual native oxide becomes a more robust form of silicon oxide.