Patent
Methods of making jfet devices with pin gate stacks
TLDR
In this paper, the authors present devices and methods for providing JFET transistors with improved operating characteristics, including a PIN gate stack and a higher diode turn-on voltage.Abstract:
Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a PIN gate stack. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.read more
Citations
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Patent
Normally-off junction field-effect transistors and application to complementary circuits
TL;DR: A junction field effect transistor (JFET) with a gate region that includes two separate sub-regions having material of different conductivity types and/or a Schottky junction that substantially suppresses gate current when the gate junction is forward-biased is described in this article.
Patent
Semiconductor devices with semiconductor bodies having interleaved horizontal portions and method of forming the devices
TL;DR: In this article, the authors present methods of forming semiconductor devices with interleaved horizontal portions, such as PN junction diodes and PIN junction Diodes, which have different conductivities and can be separated by an intrinsic semiconductor layer.
Patent
Transistors including heterogeneous channels, and related devices, electronic systems, and methods
TL;DR: In this article, the authors describe a transistor as a semiconductor device, a method of forming semiconductor devices, a memory device, and an electronic system, which is a combination of a first conductive contact, a heterogeneous channel, and a gate electrode laterally neighboring the channel.
References
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Patent
Methods of forming semiconductor constructions
TL;DR: In this paper, the authors describe semiconductor constructions containing vertically-extending pillars, and methods for forming such constructions, which can be incorporated into transistor devices, and can contain verticallyextending channel regions of the transistor devices.
Patent
Highly scalable dynamic RAM cell with self-signal amplification
TL;DR: In this paper, a memory cell comprises a substrate of a first conductivity type (preferably N type) in which is formed a first region of opposite conductivities type.
Proceedings ArticleDOI
A SiC JFET driver for a 5 kW, 150 kHz three-phase PWM converter
TL;DR: In this article, a gate driver for the SiC JFET gate was proposed to improve the switching performance by operating the gate in avalanche mode during the off time, and the proposed gate driver was shown to have a better switching performance compared to the conventional conventional SiC gate drivers.
Patent
Light-sensing device
TL;DR: In this article, a method of fabricating light-sensing devices including photodiodes monolithically integrated with CMOS devices was proposed. But the method was not implemented with epitaxially deposited films on the following substrates: Silicon Bulk, Thick-Film and Thin-Film Silicon-On-Insulator (SOI), Germanium Bulk, thick-film and thin-filtering Germanium-on-insulator (GeOI), the active areas having defined polarities.
Patent
Normally-off integrated JFET power switches in wide bandgap semiconductors and methods of making
Igor Sankin,Joseph Neil Merrett +1 more
TL;DR: In this paper, wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described, which can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single- or multi-chip wide band gap power semiconductor module.