Patent
Microprocessor having precoder unit and main decoder unit operating in pipeline processing manner
TLDR
In this article, a microprocessor having the instruction decoding operation performed by a precoder unit and a main decoder unit which operates in a pipelined manner by providing a buffer for temporarily storing information from the precoder units positioned between the precoding unit and the main decoding unit.Abstract:
A microprocessor having the instruction decoding operation performed by a precoder unit and a main decoder unit which operates in a pipelined manner by providing a buffer for temporarily storing information from the precoder unit positioned between the precoder unit and the main decoder unit. The microprocessor supports different instruction formats and operand addressing modes without lowering the instruction decoding speed.read more
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Microcode patch device and method for patching microcode using match registers and patch routines
TL;DR: In this article, a random access memory (RAM) is provided in a processor for implementing microcode patches, which is part of the normal microcode contained in a microcode read only memory (ROM) unit of the processor.
Patent
Flexible implementation of a system management mode (smm) in a processor
John G. Favor,Frederick D. Weber +1 more
TL;DR: A system management interrupt (SMI) pin (960) is connected to the processor so that a signal on the SMI pin causes the processor to enter SMM mode as mentioned in this paper.
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Risc86 instruction set
TL;DR: In this paper, an internal RISC-type instruction structure furnishes a fixed bit-length template including a plurality of defined bit fields for a plurality-of-operation (Op) formats.
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Software scheduled superscalar computer architecture
Siamak Arya,Howard G. Sachs +1 more
TL;DR: In this paper, a computing system is described in which groups of individual instructions are executed in parallel by processing pipelines, and instructions to be executed by different pipelines are supplied to the pipelines simultaneously.
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Microcode patching apparatus and method
TL;DR: In this article, a microcode patching method and apparatus for fetching microcode from an external source which, under appropriate conditions, replaces direct reading of micro code from a micro code ROM is described.
References
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Patent
Instruction processing unit for computer
TL;DR: In this paper, a computer (20) is configured for optimizing the processing rate of instructions and the throughput of data, which includes a main memory (99), a memory control unit (22), a physical cache unit (100), and a central processor (156).
Patent
Microword generation mechanism utilizing separate programmable logic arrays for first and second microwords
TL;DR: In this article, a microwave generation mechanism is presented for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed digital data processor, which includes a first programmable logic array mechanism responsive to the processor instruction to be executed for providing the first microword needed in the execution.
Patent
Pipeline structures and methods
TL;DR: In this article, a system for early decoding of complex instructions in a pipelined processor uses a programmed logic array to decode instruction segments and loads both instruction bits and the association predecoded bits into a FIFO buffer to accumulate a plurality of such entries.
Patent
Pipeline type microprocessor
Takashi Miyamori,Misao Miyata +1 more
TL;DR: In this paper, a pipeline type microprocessor has an instruction fetch unit (3), an address generation unit (9), address translation unit, and an instruction execution unit (15), which further comprises a pre-decoding unit (23) for con-verting each instruction fetched into an intermediate in-struction, the decoding operation of which is completed within a predetermined time, and a decoded instruction buffer unit (25) for temporarily storing and holding each intermediate instruction generated from the pre decoding unit, wherein the instruction decoding process is divided into two stage groups by the dec