Patent
Multi-chip module semiconductor devices
Nicolas J. Wheeler,Philip Rutter +1 more
TLDR
In this article, a multi-chip module semiconductor device with a flip-chip IC is shown to have low impedance circuit connections provided by the bump electrodes (31, 32) and strap connections (181,182).Abstract:
In a multi-chip module semiconductor device (1), at least one first semiconductor die (20) is mounted on the base portion (11) of a lead-frame (10). A flip chip IC die (30) is mounted by first bump electrodes (31) to electrode contacts (G, S() on the at least one first die (20) and by second bump electrodes (32) to terminal pins (14) of the lead frame. The integrated circuit of the flip chip (30) does not require any lead-frame base-portion area for mounting, and low impedance circuit connections are provided by the bump electrodes (31, 32). The first die (20) may be a MOSFET power switching transistor, with a gate driver circuit in the flip chip (30). The circuit impedance for the switching transistor may be further reduced by having distributed parallel gate connections (G), which may alternate with distributed parallel source connections (S(), and furthermore by having distributed and alternating power supply connections (VCC, GND). The module may comprise two series connected transistors (201, 202) and a control circuit flip chip (300), with bump electrodes (31, 32) and strap connections (181,182) for providing a dc-dc converter without any wire bonds.read more
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References
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Patent
Packaging multi-chip modules without wire-bond interconnection
TL;DR: In this paper, the MCM tiles are packaged without wire-bond interconnections and in a total thickness which is reduced relative to conventional MCM packaging, including a substrate with a plurality of peripheral metallizations and at least one chip flip-chip mounted on the substrate.
Patent
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TL;DR: In this paper, a novel packaging of semiconductor elements, such as MCM tiles, with a variety of printed circuit or wired boards (PWB), the packages occupying a small size, at least in the vertical direction, relative to prior art OMPAC devices.
Patent
Direct stacked and flip chip power semiconductor device structures
Raymond Albert Fillion,Eric Joseph Wildi,Charles Steven Korman,Sayed-Amr Ahmes El-Hamamsy,Steven M. Gasworth,Michael W. DeVre,James F. Burgess +6 more
TL;DR: In this paper, a patterned metallization layer is formed over the thermally-conductive dielectric layer, with portions of the metallisation layer extending through the vias into electrical contact with the chip contact pads.
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TL;DR: In this article, a multi-chip module (MCM) having a substrate including a first surface, a second surface and a multilayer interconnection arrangement disposed between the two surfaces is considered, where a high-density thin-film circuit region is provided on the substrate first surface to interconnect a plurality of integrated circuit chips and the multi-layer interconnect arrangement.