Patent
Offset drain fermi-threshold field effect transistors
TLDR
In this article, offset drain Fermi threshold field effect transistor (Fermi-FET) is introduced to introduce a drift region between the drain region and the FermI-Fet channel that can provide high voltage and/or high frequency FETs.Abstract:
An offset drain Fermi-threshold field effect transistor (Fermi-FET) includes spaced apart source and drain regions in an integrated circuit substrate, and a Fermi-FET channel in the integrated circuit substrate, between the spaced apart source and drain regions. A gate insulating layer is on the integrated circuit substrate between the spaced apart source and drain regions, and a gate electrode is on the gate insulating layer. The gate electrode is closer to the source region than to the drain region. Stated differently, the drain region is spaced farther away from the gate electrode than the source region. The offset drain Fermi-FET can introduce a drift region between the drain region and the Fermi-FET channel that can provide the high voltage and/or high frequency Fermi-FETs, while retaining the Fermi-FET advantages in the channel.read more
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Patent
Fin-type field effect transistor
TL;DR: In this article, improved fin-type field effect transistor (FinFET) structures and associated methods of manufacturing the structures are discussed, and an improved FinFET drive current is optimized by configuring the fin-FET asymmetrically to decrease fin resistance between the gate and the source region and to decrease capacitance in the drain region.
Patent
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References
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Patent
Fermi threshold field effect transistor
TL;DR: In this paper, the authors proposed a Fermi threshold FET with a threshold voltage that is independent of oxide thickness, channel length, drain voltage, and substrate doping, which can be manufactured using relaxed ground-rules to provide low cost, high yield devices.
Patent
Contoured-tub fermi-threshold field effect transistor and method of forming same
TL;DR: In this article, a Fermi-threshold field effect transistor includes a contoured-tub region of the same conductivity type as the source, drain and channel regions and having nonuniform tub depth.
Patent
Mis type semiconductor device
Koichi Nishiuchi,Hideki Oka +1 more
TL;DR: In this paper, a window is etched through an SiO 2 film 21 on a p-type Si 1 to produce n-layers 2 and 3 and an n-layer 10 by a diffusion.