Proceedings ArticleDOI
On the design of robust testable CMOS combinational logic circuits
Sandip Kundu,Sudhakar M. Reddy +1 more
- pp 220-225
TLDR
The authors propose an integrated approach to the design of combinational logic circuits in which stuck-open faults and path delay faults are detectable by robust tests that detect modeled faults independent of the delays in the circuit under test.Abstract:
The authors propose an integrated approach to the design of combinational logic circuits in which stuck-open faults and path delay faults are detectable by robust tests that detect modeled faults independent of the delays in the circuit under test. They demonstrate that the proposed designs and tests guarantee the design of CMOS logic circuits in which all path delay faults are locatable. >read more
Citations
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Journal ArticleDOI
Synthesis of robust delay-fault-testable circuits: theory
Srinivas Devadas,K. Keutzer +1 more
TL;DR: It is shown that constrained algebraic factorization is required to retain complete gate-delay-fault testability beginning from a two-level network.
Proceedings ArticleDOI
A cell-replicating approach to minicut-based circuit partitioning
C. Kring,A.R. Newton +1 more
TL;DR: An extension to the Fiduccia and Mattheyses minicut algorithm (1982) allows cells to be replicated in both sides of the partition and can substantially reduce the number of cut nets in a partitioned network below what can be obtained without replication.
Proceedings ArticleDOI
On the design of path delay fault testable combinational circuits
A.K. Pramanick,Sudhakar M. Reddy +1 more
TL;DR: A theoretical framework for investigating the design for the path-delay-fault testability problem is provided and a design procedure is given for the synthesis of multioutput, multilevel combinational logic circuits in which all path delay faults are robustly detectable.
Proceedings ArticleDOI
On-line delay testing of digital circuits
P. Franco,Edward J. McCluskey +1 more
TL;DR: It is shown that, under certain timing restrictions, an off-line delay-fault testing method called Stability Checking can be used for on-line checking and is shown to perform almost as well as duplication at a fraction of the hardware cost.
Proceedings ArticleDOI
Synthesis of delay fault testable combinational logic
TL;DR: The synthesis of combinational logic which is robust delay fault testable is developed and the sharing of terms in a multilevel circuit is preserved to the greatest extent possible.
References
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Book
Logic Minimization Algorithms for VLSI Synthesis
TL;DR: The ESPRESSO-IIAPL as discussed by the authors is an extension of the ESPRSO-IIC with the purpose of improving the efficiency of Tautology and reducing the number of blocks and covers.
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Switching and Finite Automata Theory
Zvi Kohavi,Niraj K. Jha +1 more
TL;DR: Theories are made easier to understand with 200 illustrative examples, and students can test their understanding with over 350 end-of-chapter review questions.
Proceedings Article
Model for Delay Faults Based Upon Paths
TL;DR: A procedure is described which identifies paths which are tested for path faults by a set of patterns, independent of the delays of any individual gate of the network, which is a global delay fault model.
Journal ArticleDOI
Fault modeling and logic simulation of CMOS and MOS integrated circuits
TL;DR: This paper provides a methodology for creating simulator models for tri-state and other dynamic circuit elements that provide for both classical and stuck-open/stuck-on faults, and can be adopted for use on essentially any general purpose logic simulator.
Journal ArticleDOI
Easily Testable Realizations ror Logic Functions
TL;DR: A realization for arbitrary logic function, using AND and EXCLUSIVE-OR gates, based on Reed-Muller canonic expansion is given that has many of these desirable properties of "easily testable networks".