Proceedings ArticleDOI
Packet Classification with Limited Memory Resources
Michal Kekely,Jan Korenek +1 more
- pp 179-183
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TLDR
A new hardware architecture for packet classification is designed, which can balance between the processing speed and hardware resources, and can scale the processing rate to wire-speed throughput on 100 Gbps line at the cost of additional memory resources.Abstract:
Network security and monitoring devices use packet classification to match packet header fields in a set of rules. Many hardware architectures have been designed to accelerate packet classification and achieve wire-speed throughput for 100 Gbps networks. The architectures are designed for high throughput even for the shortest packets. However, FPGA SoC and Intel Xeon with FPGA have limited resources for multiple accelerators. Usually, it is necessary to balance between available resources and the level of acceleration. Therefore, we have designed new hardware architecture for packet classification, which can balance between the processing speed and hardware resources. To achieve 10 Gbps average throughput the architecture need only 20 BlockRAMs for 5500 rules. Moreover, the architecture can scale the processing speed to wire-speed throughput on 100 Gbps line at the cost of additional memory resources.read more
Citations
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Proceedings ArticleDOI
Optimizing Packet Classification on FPGA
Michal Kekely,Jan Korenek +1 more
TL;DR: In this paper , the authors proposed optimizations to the DCFL algorithm and overall packet processing hardware architecture to maximize the throughput and minimize the resource strain, which can achieve up to a 76 % increase in the throughput of the packet classification.
Journal ArticleDOI
ASIC modelling of SENSE for parallel MRI
TL;DR: An Application Specific Integrated Circuits model of SENSE (a pMRI algorithm) is presented which reconstructs the image from the undersampled data right on the data acquisition module of the scanner and will open new ways for faster image reconstruction on portable MRI scanners.
References
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Proceedings ArticleDOI
Packet classification on multiple fields
Pankaj Gupta,Nick McKeown +1 more
TL;DR: It is found that a simple multi-stage classification algorithm, called RFC (recursive flow classification), can classify 30 million packets per second in pipelined hardware, or one million packetsper second in software.
Proceedings ArticleDOI
High-speed policy-based packet forwarding using efficient multi-dimensional range matching
TL;DR: New packet classification schemes are presented that, with a worst-case and traffic-independent performance metric, can classify packets, by checking amongst a few thousand filtering rules, at rates of a million packets per second using range matches on more than 4 packet header fields.
Proceedings ArticleDOI
Fast and scalable layer four switching
TL;DR: Two new algorithms for solving the least cost matching filter problem at high speeds are described, based on a grid-of-tries construction and works optimally for processing filters consisting of two prefix fields using linear space.
Proceedings ArticleDOI
Packet classification using multidimensional cutting
TL;DR: This paper introduces a classification algorithm called phHyperCuts, which can provide an order of magnitude improvement over existing classification algorithms and can be fully pipelined to provide one classification result every packet arrival time, and also allows fast updates.
Journal ArticleDOI
ClassBench: a packet classification benchmark
TL;DR: This work presents ClassBench, a suite of tools for benchmarking packet classification algorithms and devices and seeks to eliminate the significant access barriers to realistic test vectors for researchers and initiate a broader discussion to guide the refinement of the tools and codification of a formal benchmarking methodology.