Performance-Driven Simultaneous Partitioning and Routing for Multi-FPGA Systems
Ming-Hung Chen,Yao-Wen Chang,Jun-Jie Wang +2 more
- pp 1129-1134
TLDR
In this article, a routing-aware partitioning and routing algorithm for multi-FPGA systems is proposed to optimize the performance of such a system considering the timing penalty caused by I/O TDM.Abstract:
A multi-FPGA system consists of multiple FPGAs connected by physical wires, and a circuit is partitioned to fit each FPGA and routed on the system by such physical wires. Due to the limited numbers of input/output (I/O) pins in an FPGA, however, not all signals can be transmitted between FPGAs directly. Moreover, the routing resource may not be sufficient to accommodate many cross-FPGA signals from circuit partitioning. As a result, input/output time-division multiplexing (TDM) is introduced to send a group of cross-FPGA signals in a routing channel with a timing penalty. To optimize the performance of such a system, we shall develop a simultaneous partitioning and routing algorithm considering the timing penalty caused by I/O TDM. Considering the TDM delay penalty, we propose a simultaneous partitioning and routing algorithm to remedy the insufficiency of the two-stage flow of partitioning followed by routing. Our algorithm consists of two major steps: (1) a novel routing-aware partitioning framework to obtain an initial solution considering irregular, asymmetric connections, and (2) a partition-aware routing scheme to optimize routing in each partitioning pass. Experimental results show that our proposed algorithm can achieve better timing than the classical flow.read more
Citations
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Journal ArticleDOI
A Hypergraph Model and Associated Optimization Strategies for Path Length-Driven Netlist Partitioning
TL;DR: In this article , the authors propose a hypergraph model for initial partitioning and partition refinement, and integrate these algorithm in a multilevel framework, combined with existing min-cut solvers, to tackle simultaneously both path length and cut size objectives.
Proceedings ArticleDOI
SPARK: A Scalable Partitioning and Routing Framework for Multi-FPGA Systems
TL;DR: SPARK as mentioned in this paper is a scalable partitioning and routing framework for multi-FPGA systems with an adjustable near-square mesh shape and the minimum number of FPGAs, which leverages the general hypergraph partitioning tool by combining it with an efficient legalization algorithm to minimize cut size without resource overflow.
Proceedings ArticleDOI
CPP: A Multi-Level Circuit Partitioning Predictor for Hardware Verification Systems
TL;DR: Chen et al. as mentioned in this paper use circuit coarsening to develop a multi-level path representation and employ a convolutional neural network (CNN) that can capture both local and global path structures for delay prediction.
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