Available on CMS information server CMS CR -2020/014
The Compact Muon Solenoid Experiment
Mailing address: CMS CERN, CH-1211 GENEVA 23, Switzerland
Conference Report
20 January 2020 (v3, 13 February 2020)
Performance study of HGCROC-V2: the front-end
electronics for the CMS High Granularity
Calorimeter
Damien Thienpont for the CMS Collaboration
Abstract
The High Granularity Calorimeter (HGCAL), presently being designed by the Compact Muon Solenoid
collaboration (CMS) to replace the existing endcap calorimeters for the High Luminosity phase of
the LHC, will feature unprecedented transverse and longitudinal readout and triggering segmentation
for both electromagnetic and hadronic sections. The requirements for the front-end electronics are
extremely challenging, including high dynamic range (0-10 pC), low noise ( 2000 electrons), high-
precision timing information in order to mitigate the pileup effect (25 ps binning) and low power con-
sumption ( 15 mW/channel). The front-end electronics will face a harsh radiation environment which
will reach 200 Mrad at the end of life. It will work at a controlled temperature of 240 K. HGCROV-V2
is the second prototype of the front-end ASIC. It has 72 channels of the full analog chain: low noise
and high gain preamplifier and shapers, and a 10-bit 40 MHz SAR-ADC, which provides the charge
measurement over the linear range of the preamplifier. In the saturation range of the preamplifier, a
discriminator and TDC provide the charge information from TOT (Time Over Threshold) over 200 ns
dynamic range using 50 ps binning. A fast discriminator and TDC provide timing information to 25
ps accuracy. Both charge and timing information are kept in a DRAM memory waiting for a Level
1-trigger decision (L1A). At a bunch crossing rate of 40 MHz, compressed charge data are sent out to
participate in the generation of the L1-trigger primitives. We report on the performances of the chip in
terms of signal-to-noise ratio, charge and timing, as well as results from radiation qualification with
total ionizing dose (TID).
Presented at CHEF2019 Calorimetry for the High Energy Frontier 2019
Performance study of HGCROC-v2: the front-end
electronics for the CMS High Granularity
Calorimeter
D. Thienpont
a
,
*
C. de La Taille
a
on behalf of the CMS Collaboration
a
OMEGA/CNRS/Ecole Polytechnique
Ecole Polytechnique, bât. 404
Route de Saclay
91120 PALAISEAU, FRANCE
E-mail: damien.thienpont@in2p3.fr
ABSTRACT: The High Granularity Calorimeter (HGCAL), presently being designed by the
Compact Muon Solenoid collaboration (CMS) to replace the existing endcap calorimeters for the
High Luminosity phase of the LHC, will feature unprecedented transverse and longitudinal
readout and triggering segmentation for both electromagnetic and hadronic sections. The
requirements for the front-end electronics are extremely challenging, including high dynamic
range (0-10 pC), low noise (~2000 electrons), high-precision timing information in order to
mitigate the pileup effect (25 ps binning) and low power consumption (~15 mW/channel). The
front-end electronics will face a harsh radiation environment which will reach 200 Mrad at the
end of life. It will work at a controlled temperature of 240 K.
HGCROV-V2 is the second prototype of the front-end ASIC. It has 72 channels of the full analog
chain: low noise and high gain preamplifier and shapers, and a 10-bit 40 MHz SAR-ADC, which
provides the charge measurement over the linear range of the preamplifier. In the saturation range
of the preamplifier, a discriminator and TDC provide the charge information from TOT (Time
Over Threshold) over 200 ns dynamic range using 50 ps binning. A fast discriminator and TDC
provide timing information to 25 ps accuracy. Both charge and timing information are kept in a
DRAM memory waiting for a Level 1-trigger decision (L1A). At a bunch crossing rate of 40
MHz, compressed charge data are sent out to participate in the generation of the L1-trigger
primitives.
We report on the performances of the chip in terms of signal-to-noise ratio, charge and timing, as
well as results from radiation qualification with total ionizing dose (TID).
KEYWORDS: CMS HGCAL; electronics for detector readout; timing detector; performance.
*
Corresponding author.
– 1 –
Contents
1. Introduction 1
2. Architectural overview 1
3. Performance study 2
3.1 General performance 3
3.1.1 Noise performance 3
3.1.2 Charge measurement performance 4
3.1.3 Time measurement performance 6
3.2 Specific performance 6
3.2.1 Temperature sensitivity 6
3.2.2 TID results 6
4. Conclusion 6
1. Introduction
As described in [1], the entire electromagnetic section and part of the hadronic section of the
HGCAL consist of hexagonal silicon sensors while the rest of the hadronic section in the lower
radiation region will be made of SiPM-on-scintillator tiles. The SiPM-readout chip is made by
only adding a current conveyor and adapting the preamplifier of the silicon version. This paper
focuses on the architecture and performance of the latter.
2. Architectural overview
The HGCROC-V2 chip is made of: 72 channels of the full analog chain achieving charge
and timing information; 4 common mode channels for subtracting coherent noise; 2 calibration
channels for the MIP calibration. Four 1.28 Gbps links are devoted to send out an image of the
deposited charge of each bunch crossing event by summing and compressing data over 4 (or 9)
channels. These data will contribute to the L1 trigger generation. Two more 1.28 Gbps links are
dedicated to send out the full event information (charge and time) of selected bunch crossings
after a L1 trigger request.
The I2C protocol is used to set or read the more than 7900 parameters of the chip. This part
is triplicated to resist to the Single Event Effect (SEE). The chip is controlled by the Fast
Command block which receives a clock and a command link at 320 MHz. This allows to configure
the operating mode of the system: link synchronization, reset, calibration, L1 request, etc. The 40
MHz clock, in phase with the LHC clock, is extracted from the 320 MHz fast command link and
provides the clock to the digital part of the ASIC (digital processing, I2C) and to the PLL which
generates the others clocks needed to operate the chip: the 640 MHz clock for the 1.28 Gbps links,
– 2 –
the phase adjustable 40 MHz clock for the ADCs, the phase adjustable 160 MHz clock for the
TDCs. Indeed it is needed to be able to adjust the phase of the conversion blocks (ADC and TDC)
to the phase of the physical signals which depend on the rapidity angle.
Figure 1: architectural overview of HGCROC-V2
The analog front-end is made of three distinct sub-parts:
- The low-noise preamplifier which converts the input charge from the silicon diode into an
output voltage. As the value of the MIP depends on the sensor thickness and on the irradiation,
the preamplifier gain is programmable so that the ADC range covers an energy range
corresponding to 100 times the energy deposited by a minimum ionizing particle (MIP). A
specific requirement is also not to have more than 20% of the signal in the next bunch crossing
in order to mitigate the pile-up effect: this is achieved by the preamplifier constant time
feedback.
- The shaper is made of three stages: a first gain-2 Sallen-Key shaper; a gain-3 RC² shaper; a
unity gain buffer to drive the signal to the ADC.
- A discriminator provides the charge measurement when the preamplifier saturates by using
the Time Over Threshold (TOT) technique. Another one provides the timing information by
measuring the Time Of Arrival (TOA).
The charge information is given by the 10-bit SAR ADC (see [2]) in the linear range of the
preamplifier. A dedicated 10-bits TDC measures the time of the TOA discriminator. Another 12-
bits TDC measures the time of the second edge of the TOT discriminator which gives the charge
information when the preamplifier saturates by subtracting the TOT time and the TOA time.
3. Performance study
A first characterization board has been developed where the chip is flipped on a mezzanine; all
the power supplies remain separated (7 analog and 4 digital). This version makes it possible to
check the performance of the circuit in an optimistic framework since the possible couplings via
the power supplies are reduced. With this board, no coupling of the digital part appears on the
signals converted by the ADCs as shown in Figure 2. The noise measured on the pedestals is
around 1 ADC unit.
Another board has been developed to validate the operation of the circuit in a BGA. Here,
the power supplies are all combined to leave only two global power supplies: one for the analog
– 3 –
domain and another for the digital domain. We now observe a coupling of the digital clock on the
waveforms. The effective noise is only slightly higher (1.25 ADC unit), which is normal since the
ADCs sample the signal at constant phase compared to that of the digital domain. It is the reason
why this coupling does not disturb the charge measurement of the ADCs. But this is not the case
for the TOA and TOT measurements since the edges of the discriminators will arrive
asynchronously with respect to the global clock.
The difference found is attributed to the grounding of the BGA lead frame, which will be corrected
in the future.
Figure 2: on the left hand side, the "FlipChip" board, waveforms and noise; on the right hand side, the
"BGA" board, waveforms and noise.
3.1 General performance
A calibration pulser, based on an 11-bit DAC, has been integrated into the chip to emulate a
charge injection (up to 8 pC). The measured performance shows a good linearity of +/- 0.1% of
the full dynamic range. But with an unexpected offset of around 30 mV, limiting the minimum
charge to be injected to ~ 15 fC (5 – 10 MIPs) whilst 0 fC was expected. This is due to the fact
that the calibration DAC ground has been tied to the reference voltage grounding rather than the
preamplifier ground: this will be easily corrected in the future.
3.1.1 Noise performance
An important parameter is the noise performance of the chip. The series noise whose main
contributor is the input transistor of the preamplifier depends on the detector capacitance value.
The measurements show a series noise of 0.7 nV/√Hz and a preamplifier input capacitance of 6
pF in accordance with the simulations and the specifications.
In the final system, the high voltage, needed to bias the silicon sensor, could be an important
coherent noise source. It is so required to keep as low as possible all sources of coherent noise of
the chip itself. By comparing direct (DS = ∑ ch[i]) and alternate (AS = ∑ (-1
i
) ch[i]) sums of the
72 channels, the incoherent (IN = rms(AS)/√n) and coherent (CN = √[var(DS)-var(AS)]/n) noises
may be extracted. We find 5% of coherent noise for the flipchip board and 10% for the BGA
board.
