PLRU Cache Domino Effects
Christoph Berg
- Vol. 4, pp 0
TLDR
This paper shows that the pseudo LRU (PLRU) cache replacement policy can cause unbounded effects on the WCET, which is widely used in embedded systems, and some x86 models.Abstract:
Domino effects have been shown to hinder a tight prediction of worst case execution times (WCET) on real-time hardware. First investigated by Lundqvist and StenstrAƒÂ¶m, domino effects caused by pipeline stalls were shows to exist in the PowerPC by Schneider. This paper extends the list of causes of domino effects by showing that the pseudo LRU (PLRU) cache replacement policy can cause unbounded effects on the WCET. PLRU is used in the PowerPC PPC755, which is widely used in embedded systems, and some x86 models.read more
Citations
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Journal ArticleDOI
Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-Critical Embedded Systems
Reinhard Wilhelm,Daniel Grund,Jan Reineke,Marc Schlickling,Markus Pister,Christian Ferdinand +5 more
TL;DR: The architectural influence on static timing analysis is described and recommendations as to profitable and unacceptable architectural features are given and results show that measurement-based methods still used in industry are not useful for quite commonly used complex processors.
Journal ArticleDOI
Building timing predictable embedded systems
Philip Axer,Rolf Ernst,Heiko Falk,Alain Girault,Daniel Grund,Nan Guan,Bengt Jonsson,Peter Marwedel,Jan Reineke,Christine Rochange,Maurice Sebastian,Reinhard von Hanxleden,Reinhard Wilhelm,Wang Yi +13 more
TL;DR: The intention of this article is to summarize the current state of the art in research concerning how to build predictable yet performant systems, and suggest precise definitions for the concept of “predictability”, and present predictability concerns at different abstraction levels in embedded system design.
Proceedings ArticleDOI
A Unified WCET Analysis Framework for Multi-core Platforms
Sudipta Chattopadhyay,Chong Lee Kee,Abhik Roychoudhury,Timon Kelter,Peter Marwedel,Heiko Falk +5 more
TL;DR: This work differs by modeling the interaction of shared cache and shared bus with other basic micro-architectural components (e.g. pipeline and branch predictor) by assuming a timing anomaly free multi-core architecture for computing the WCET.
Proceedings ArticleDOI
METAMOC: Modular Execution Time Analysis using Model Checking
Andreas Engelbredt Dalsgaard,Mads Chr. Olesen,Martin Toft,René Rydhof Hansen,Kim Guldstrand Larsen +4 more
TL;DR: Experiments on the Malardalen WCET benchmark programs show that taking caching into account yields much tighter WCETs than without modelling caches, and that METAMOC is a suciently fast and versatile approach for WCET analysis.
Proceedings ArticleDOI
Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison
Isabelle Puaut,Christophe Pais +1 more
TL;DR: Experimental results show that the algorithm yields to good ratios of on-chip memory accesses on the worst-case execution path, with a tolerable reload overhead, for both types of on -chip memories.
References
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Proceedings ArticleDOI
Timing anomalies in dynamically scheduled microprocessors
Thomas Lundqvist,Per Stenström +1 more
TL;DR: This work provides necessary conditions when timing anomalies can show up and identifies what architectural features that may cause such anomalies, and proposes some simple code modification techniques to make it impossible for any anomalies to occur.
Journal ArticleDOI
The influence of processor architecture on the design and the results of WCET tools
TL;DR: The designs of WCET tools for a series of increasingly complex processors, including SuperSPARC, Motorola ColdFire 5307, and Motorola PowerPC 755, are described, and some advice is given as to the predictability of processor architectures.
Proceedings ArticleDOI
A Definition and Classification of Timing Anomalies
Jan Reineke,Björn Wachter,Stephan Thesing,Reinhard Wilhelm,Ilia Polian,Jochen Eisinger,Bernd Becker +6 more
TL;DR: One of these classes of anomalies, coined Scheduling Timing Anomalies, coincides with previous restricted definitions and is given a concise formal definition.
Dissertation
A WCET Analysis Method for Pipelined Microprocessors with Cache Memories
TL;DR: This thesis presents a new method, referred to as cycle-level symbolic execution , that tightly integrates path and timing analysis and automatically eliminates infeasible paths and derives path information such as loop bounds, and performs accurate timing analysis for a multiple-issue processor with an instruction and data cache.