Journal ArticleDOI
Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme
Reads0
Chats0
TLDR
A novel dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme that is suitable for low-power applications in very-large-scale integration (VLSI) designs with low data-switching activities is proposed.Abstract:
A novel dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme (DIFF-CGS) is proposed, which employs a transmission-gate-logic (TGL) based clock-gating scheme in the pulse generation stage. This scheme condi- tionally disables the inverter chain when the input data are kept unchanged, so redundant transitions of delayed clock signals and internal nodes of the latch are all eliminated, leading to low power efficiency. Based on SMIC 65 nm technology, extensive post-layout simulation results show that the proposed DIFF-CGS gains an improvement of 41.39% to 56.21% in terms of power consumption, compared with its counterparts at 10% data-switching activity. Also, full-swing operations in both implicit pulse generation and the static latch improve the robustness of the design. Thus, DIFF-CGS is suitable for low-power applications in very-large-scale integration (VLSI) designs with low data-switching activities.read more
Citations
More filters
Book ChapterDOI
A Novel Survey on Ubiquitous Computing
TL;DR: In this article , the exact issues and limitations that are stopping Ubicomp from becoming a reality are identified and discussed, along with potential solutions to them, which are being rapidly developed.
Journal ArticleDOI
Design and Analysis of A 32-bit Pipelined MIPS Risc Processor
TL;DR: The 32-bit MIPS RISC processor is used in 6-stage pipelining to optimize the critical performance factors and achieves better frequency increase, which obtained better results compared to other models.
Proceedings ArticleDOI
Five Stage Pipelined MIPS Processor Verification Interface and Test Module using UVM
TL;DR: In this article , a five-stage pipelined MIPS processor with 16 instructions with a total of 49 variants, 5 pipeline stages, and a hazard unit is tested using constrained random verification and for implementing verification techniques in System Verilog Unified Verification Methodology.
Proceedings ArticleDOI
Five Stage Pipelined MIPS Processor Verification Interface and Test Module using UVM
TL;DR: In this paper , a five-stage pipelined MIPS processor with 16 instructions with a total of 49 variants, 5 pipeline stages, and a hazard unit is tested using constrained random verification and for implementing verification techniques in System Verilog Unified Verification Methodology.
Journal ArticleDOI
Design and Implementation of Enhanced Edge Triggered Flip-Flop for Low Power Dissipation
TL;DR: In this paper , the authors proposed an enhanced dual edge triggered flip-flop (2EdTFF) based on robust pass-transistor logic (PTL) for power consumption reduction.
References
More filters
Book
CMOS VLSI Design : A Circuits and Systems Perspective
Neil Weste,David Money Harris +1 more
TL;DR: The authors draw upon extensive industry and classroom experience to introduce todays most advanced and effective chip design practices, and present extensively updated coverage of every key element of VLSI design, and illuminate the latest design challenges with 65 nm process examples.
Journal ArticleDOI
Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems
TL;DR: A new simulation and optimization approach is presented, targeting both high-performance and power budget issues, and the analysis approach reveals the sources of performance and power-consumption bottlenecks in different design styles.
Journal ArticleDOI
A reduced clock-swing flip-flop (RCSFF) for 63% power reduction
TL;DR: A reduced clock-swing flip-flop (RCSFF) is proposed, which is composed of a reduced swing clock driver and a special flip- flop which embodies the leakage current cutoff mechanism.
Journal ArticleDOI
Clock-gating and its application to low power design of sequential circuits
Qing Wu,Massoud Pedram,Xunwei Wu +2 more
TL;DR: In this paper, the clock behavior in a sequential circuit is modeled by a quaternary variable and two clock-gating techniques are proposed to generate clock synchronous with the master clock.
Journal ArticleDOI
High-performance and low-power conditional discharge flip-flop
TL;DR: In this paper, high-performance flip-flops are analyzed and classified into two categories: the conditional precharge and the conditional capture technologies, based on how to prevent or reduce the redundant internal switching activities.
Related Papers (5)
Clock Gated Single-Edge-Triggered Flip-Flop Design with Improved Power for Low Data Activity Applications
Imran Khan,Mirza Tariq Beg +1 more