Proceedings ArticleDOI
Power Optimized Digital Decimation Filter for Medical Applications
Bijoy Babu,K.N. Shesharaman,Harish M. Kittur +2 more
- pp 90-93
TLDR
In this article, a digital decimation filter for medical applications (NMRI) is designed and proposed in this paper, which is based on Cascaded Integrated Comb (CIC) filter architecture.Abstract:
A digital decimation filter for medical applications (NMRI) is designed and proposed in this paper. The digital decimation filter is one of the main blocks of ?-? ADC .For a clinical NMRI systems, the resonating frequency being 64MHz for a magnetic field strength of 1.5 T. The decimation filter down samples the over sampled output of the ?-? modulator to Nyquist sampling rate of 128MHz.. The power, speed and the area of operation are largely governed by decimation filters in ?-? ADC. The digital decimation filter is based on Cascaded Integrated Comb (CIC) filter architecture. In this scheme the optimization of the two stage CIC structure is done and the power consumption is considerably reduced compared to the conventional CIC filter architectures. The proposed resolution filter is realised in 0.18µm CMOS technology which occupies an area of 0.088mm2and consumes a power of 2.67mW from a 1.5V supply.read more
Citations
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Journal ArticleDOI
Design of Five Stage CIC Decimation Filter for Signal Processing Applications
D. Sabitha,K. Hariharan +1 more
TL;DR: The five stage CIC filter is proposed in this paper, which does not require any multiplier circuit and also uses recursive or non-recursive filter[4].
Journal ArticleDOI
Implement Multichannel Fractional Sample Rate Convertor using Genetic Algorithm
Vivek Jain,Navneet Agrawal +1 more
TL;DR: Power of multichannel fractional sample rate convertor is reduced by minimized hamming distance between consecutive coefficients of filter using Genetic algorithm which reduces the switching activity of CMOS transistor and minimizes the total power consumption.
Journal ArticleDOI
Low power cic filter design for delta sigma adc
Siva Kumaaran,Lee Lini +1 more
TL;DR: The True Single Phase Clocked D-Flip Flop, which is made up of split-output latches, was applied as the register, instead of conventional D-flip Flops, and displayed a significant reduction in power consumption.
Proceedings ArticleDOI
A Low Power 15-Bit Decimator in 0.18um CMOS for Biomedical Applications
TL;DR: A low power design for a decimator as part of a sigma-delta ADC for biomedical application in a commercial 0.18um CMOS process makes use of a bit-serial architecture.
References
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Book
Delta-sigma data converters : theory, design, and simulation
TL;DR: Delta-Sigma Data Converters provides comprehensive coverage of low and high-order single-bit, bandpass, continuous-time, multistage modulators as well as advanced topics, including idle-channel tones, stability, decimation and interpolation filter design, and simulation.
Journal ArticleDOI
An economical class of digital filters for decimation and interpolation
TL;DR: A class of digital linear phase finite impulse response (FIR) filters for decimation and interpolation and use limited storage making them an economical alternative to conventional implementations for certain applications.
Journal ArticleDOI
A new two-stage sharpened comb decimator
TL;DR: The proposed realization scheme allows the sharpened section to operate at a lower rate that depends on the decimation factor of the first section and using a polyphase decomposition, the subfilters of the second section can also be operated at this lower rate.
Proceedings ArticleDOI
Low Power Non-Recursive Decimation Filters
Chi Zhang,E. Ofner +1 more
TL;DR: This work proposes low power non-recursive decimation filters in a GSM and UMTS dual mode sigma delta ADC and an alternative to the standard CIC (cascaded integrator-comb) approach with a decimation factor of m-th power of two and m- fourth power of three.
Proceedings ArticleDOI
A programmable oversampling sigma-delta analog-to-digital converter
Ashok Srivastava,R.R. Anantha +1 more
TL;DR: An oversampling sigma-delta analog-to-digital converter (ADC) has been designed and implemented in 1.5 mum n-well CMOS process using a 1st order modulator and a 2nd order cascaded integrator comb (CIC) decimation filter.