Power supply noise control in pseudo functional test
Tengteng Zhang,Duncan M. Walker +1 more
- pp 1-6
TLDR
A simulation-based X'Filling method, Bit-Flip, is proposed to maximize the power supply noise during PKLPG test and demonstrates that the method can significantly increase effective WSA while limiting the fill rate.Abstract:
Pseudo functional K Longest Path Per Gate (KLPG) test (PKLPG) is proposed to generate delay tests that test the longest paths while having power supply noise similar to that seen during normal functional operation. Our experimental results show that PKLPG is more vulnerable to under-testing than traditional two-cycle transition fault test. In this work, a simulation-based X'Filling method, Bit-Flip, is proposed to maximize the power supply noise during PKLPG test. Given a set of partially-specified scan patterns, random filling is done and then an iterative procedure is invoked to flip some of the filled bits, to increase the effective weighted switching activity (WSA). Experimental results on both compacted and uncompacted test patterns are presented. The results demonstrate that our method can significantly increase effective WSA while limiting the fill rate.read more
Citations
More filters
Proceedings ArticleDOI
Improved power supply noise control for pseudo functional test
Tengteng Zhang,Duncan M. Walker +1 more
TL;DR: A PSN control method for pseudo functional test that combines random flipping and background patterns to efficiently fill don't care bits is presented that achieves worst-case realistic PSN in significantly less CPU time than prior techniques.
Journal ArticleDOI
Close-to-Functional Broadside Tests With a Safety Margin
TL;DR: A combined metric is suggested, where a reduced switching activity is taken as a safety margin that allows a higher Hamming distance between the scan-in state and a reachable state.
Journal ArticleDOI
Partially Invariant Patterns for LFSR-Based Generation of Close-to-Functional Broadside Tests
TL;DR: The article describes a procedure for extracting partially invariant patterns from functional broadside tests whose scan-in states are reachable states and addresses the selection of LFSRs for the generation of close-to-functional broadside Tests based on partially invariants patterns.
Proceedings ArticleDOI
Functional Broadside Test Generation Using a Commercial ATPG Tool
TL;DR: The results demonstrate that it is possible to generate functional broadside tests without requiring any modifications to the commercial tool, and using the tests that the tool produces to obtain reachable states is expected to enable the generation of functionalbroadside tests for state-of-the-art designs that cannot be handled by academic tools.
References
More filters
Book
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
TL;DR: This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time- to-volume.
Proceedings ArticleDOI
Adapting scan architectures for low power operation
TL;DR: A method of adapting conventional scan architectures such that they operate in a low power mode during test so that they maintain the test times of the pre-adapted scan architectures.
Proceedings ArticleDOI
Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs
TL;DR: Experimental results presented for benchmark and industrial circuits demonstrate the effectiveness of the proposed method called Preferred Fill to reduce average and peak power dissipation during capture cycles of launch off capture delay fault tests.
Proceedings ArticleDOI
Low-capture-power test generation for scan-based at-speed testing
Xiaoqing Wen,Y. Yamashita,Shohei Morishima,Seiji Kajihara,Laung-Terng Wang,Kewal K. Saluja,Kozo Kinoshita +6 more
TL;DR: A novel low-capture-power X-filling method of assigning 0's and 1's to unspecified (X) bits in a test cube obtained during ATPG to improve the applicability of scan-based at-speed testing by reducing the risk of test yield loss.
Proceedings ArticleDOI
K longest paths per gate (KLPG) test generation for scan-based sequential circuits
Wangqi Qiu,Jing Wang,Duncan M. Walker,D. Reddy,Xiang Lu,Zhuo Li,Weiping Shi,Hari Balachandran +7 more
TL;DR: Experiments show that testing transition faults through the longest paths can be done in reasonable test set size and the test generation efficiency is evaluated on ISCAS89 benchmark circuits and industrial designs.
Related Papers (5)
Frequency and Power Correlation between At-Speed Scan and Functional Tests
S. Sde-Paz,E. Salomon +1 more