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Patent

Process for making a buried conductor by fusing two wafers

TLDR
In this paper, the authors propose a process for bonding two wafers together to form a single wafer with a continuous interface, and for selectively burying a low impedance conductor in the wafer, by providing host and guest wafer having substantially the same crystal orientation and periodicity.
Abstract
A process, and product made thereby, for bonding two wafers together to form a single wafer with a continuous interface, and for selectively burying a low impedance conductor in the wafer, by providing host and guest wafers having substantially the same crystal orientation and periodicity. A crystalline boundary n-semimetal is formed on the wafers, which are then brought into intimate contact. If desired, a unipolar conductor is fused to one of said wafers. Then, the wafers are exposed to an elevated temperature, or rapid thermal anneal, in an inert ambient, breaking up any native oxides and diffusing any excess oxygen into the wafer lattices. The guest wafer is then mechanically lapped back and chemically etched. A vertical cascode integrated half H-bridge motor driving circuit made in the guest and host wafers has a source transistor in the host wafer with with the wafer substrate forming the collector of the transistor, an isotype acceptor doped Ge x Si l-x /Si superlattice forming the base, and an overlying a monocrystalline silicon layer forming a compositional emitter, and with an n-semimetal boundary. The sink transistor of the guest is made with the wafer substrate forming the emitter, an isotype acceptor doped Ge x Si l-x /Si superlattice forming the base, and an overlying a monocrystalline silicon layer forming the compositional collector. The guest substrate is terminated with an n-semimetal boundary. A buried conductor contacts the collector of the host transistor and the emitter of the guest transistor.

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Packaging of integrated circuits and vertical integration

TL;DR: In this paper, a first level packaging wafer (110) is made of a semiconductor or insulating material, and the bumps (150B) on the wafer are made using vertical integration technology, without solder or electroplating.
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TL;DR: In this paper, a first layer and a second layer of layer-transferred mono-crystallized silicon, where the first layer comprises a first plurality of horizontally-oriented transistors, and the second layer includes a second plurality of vertically oriented transistors.
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TL;DR: In this article, a method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a metal layer overlaying the first layer and providing at least one connection to the first Transistors, and finally processing a second layer of second transistors overlaying a first metal layer, wherein the second metal layer is connected to provide power to at least 1 of the second Transistors.
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Strained Si/SiGe layers on insulator

TL;DR: An SOI substrate and method for forming is described in this article, incorporating the steps of forming strained layers of Si and/or SiGe on a first substrate, forming a layer of Si or Si O2 over the strained layers, bonding a second substrate having an insulating layer on its upper surface to the top surface above the strained layers, and removing the first substrate.
References
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Patent

Process for fabricating three-dimensional semiconductor device

TL;DR: In this article, a process of fabricating a three-dimensional semiconductor device, comprising the steps of preparing at least two multilayer structures each including at least one semiconductor element and a conductor connected at one end to the semiconductor elements and having at the other end an exposed surface, is described.
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TL;DR: In this article, a method of manufacturing a semiconductor substrate having a modified layer therein comprises the steps of mirror-polishing one surface of each of first and second semiconductor plates (21,23), forming the modified layer (22) on at least one of the polished surfaces of the first, second, and third semiconductor plate surfaces, and bonding them with each other in a clean atmosphere.
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