Journal ArticleDOI
Serial-parallel FFT array processor
J. You,S. Simon Wong +1 more
TLDR
An array architecture for computing a fast Fourier transform (FFT) with a flexible number of identical processing elements is presented and shows that a high-radix, lengthy FFT can be efficiently implemented with simple hardware.Abstract:
An array architecture for computing a fast Fourier transform (FFT) with a flexible number of identical processing elements is presented. The architecture is based on the symmetry of a constant geometry FFT. It allows an easy tradeoff between the hardware complexity and the computation time. A method for constructing a high-radix FFT with simple lower-radix hardware based on successive decompositions and premultiplications has been developed. It shows that a high-radix, lengthy FFT can be efficiently implemented with simple hardware. To verify the architecture, an experimental radix-2 processing element chip has been designed and the results are discussed. >read more
Citations
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Journal ArticleDOI
One- and two-dimensional constant geometry fast cosine transform algorithms and architectures
TL;DR: This paper presents general radix one- and two-dimensional (1-D and 2-D) constant geometry fast cosine transform algorithms and architectures suitable for VLSI, owing to their regular structures.
Journal ArticleDOI
Distributed arithmetic realisation of cyclic convolution and its DFT application
TL;DR: The authors present a new hardware-efficient group distributed arithmetic (GDA) design approach for the one-dimensional (1-D) discrete Fourier transform (DFT) that can reduce the delay–area product by 29%–68% based on a 0.35 μm CMOS cell library.
Journal ArticleDOI
Real-time implementation of the split-radix FFT - an algorithm to efficiently construct local butterfly modules
Pei-Chen Lo,Yu-Yun Lee +1 more
TL;DR: A new technique of real-time Fourier spectral analysis based on the decimation-in-time split-radix fast-Fourier-transform (DIT sr-FFT) butterfly structure provides a practical, useful approach to analyzing the on-line, time-varying Fourier spectra for the multi-channel electrophysiological signals.
Journal ArticleDOI
A parallel architecture for the self-sorting FFT algorithm
TL;DR: This work proposes a parallel architecture that implements the SS radix r (r ≥ 2) algorithm, a highly efficient version of the fast Fourier transform, that is regular and modular, and presents constant geometry.
Journal ArticleDOI
A novel algorithm for computing the 2D split-vector-radix FFT
TL;DR: The modularizing feature of the 2D svr-FFT structure enables us to explore its characteristics by identifying the local structural property, and it is shown that the distribution of DFT blocks can be illustrated by the Sierpinski triangle.
References
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Wafer-scale integration and two-level pipelined implementations of systolic arrays
Hsiang-Tsung Kung,Monica S. Lam +1 more
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Proceedings ArticleDOI
A high performance single chip FFT array processor for wafer scale integration
Jaehee You,S. Simon Wong +1 more
TL;DR: A methodology to realize a high radix processing element with lower radix hardware is presented and an experimental processor chip to implement a radix 2, 8 point FFT has been successfully designed in CMOS and the results are discussed.
Proceedings ArticleDOI
Prime Factor DFT parallel processor using wafer scale integration
Edward T. Chow,Dan I. Moldovan +1 more
TL;DR: A high speed, flexible, simple and regular Discrete Fourier Transform (DFT) Array Processor architecture based on the Prime Factor Algorithm (PFA) is presented in this paper.
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