Slope propagation in static timing analysis
David Blaauw,Vladimir Zolotov,Savithri Sundareswaran,Chanhee Oh,Rajendran Panda +4 more
- pp 338-343
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The results show that the traditional timing analysis method underestimates the circuit delay by as much as 38%, while that the proposed method efficiently finds the correct circuit delay with only a slight increase in run time.Abstract:Â
Static timing analysis has traditionally used the PERT method for identifying the critical path of a digital circuit Due to the influence of the slope of a signal at a particular node on the subsequent path delay, an earlier signal with a signal slope greater than the slope of the later signal may result in a greater delay Therefore, the traditional method for timing analysis may identify the incorrect critical path and report an optimistic delay for the circuit We show that the circuit delay calculated using the traditional method is a discontinuous function with respect to transistor and gate sizes, posing a severe problem for circuit optimization methods We propose a new timing analysis algorithm which resolves both these issues The proposed algorithm selectively propagates multiple signals through each timing edge in cases where there exists ambiguity regarding which arriving signal represents the critical path The algorithm for propagating the corresponding required times is also presented We prove that the proposed algorithm identifies a circuit's true critical path, where the traditional timing analysis method may not We also show that under this method circuit delay and node slack are continuous functions with respect to a circuit's transistor and gate sizes In addition, we present a heuristic method which reduces the number of signals to be propagated at the expense of a slight loss in accuracy Finally, we show how the proposed algorithm was efficiently implemented in an industrial static timing analysis and optimization tool, and present results for a number of industrial circuits Our results show that the traditional timing analysis method underestimates the circuit delay by as much as 38%, while that the proposed method efficiently finds the correct circuit delay with only a slight increase in run timeread more
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References
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TILOS: A posynomial programming approach to transistor sizing
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Computation of floating mode delay in combinational circuits: theory and algorithms
TL;DR: The authors introduce the notion of static cosensitization of paths which leads to necessary and sufficient conditions for determining the truth or falsity of a single path, or a set of paths.
Proceedings ArticleDOI
Formulation of static circuit optimization with reduced size, degeneracy and redundancy by timing graph manipulation
TL;DR: A method of manipulating the timing formulation is presented which produces a dramatically more compact optimization problem, and reduces redundancy and degeneracy, and the circuit optimization is therefore more efficient and effective.