Journal ArticleDOI
Random-pattern coverage enhancement and diagnosis for LSSD logic self-test
E. B. Eichelberger,E. Lindbloom +1 more
TLDR
Embedded linear feedback shift registers can be used for logic component self-test and a procedure that supports net-level diagnosis for structured logic in the presence of random test-pattern generation and signature analysis is given.Abstract:
Embedded linear feedback shift registers can be used for logic component self-test. The issue of test coverage is addressed by circuit modification, where necessary, of random-pattern-resistant fault nodes. Also given is a procedure that supports net-level diagnosis for structured logic in the presence of random test-pattern generation and signature analysis.read more
Citations
More filters
Book
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
TL;DR: This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time- to-volume.
Journal ArticleDOI
Transition Fault Simulation
TL;DR: The authors present a model, called a transition fault, which when used with parallel-pattern, single-fault propagation, is an efficient way to simulate delay faults and shows that delay fault simulation can be done of random patterns in less than 10% more time than needed for a stuck fault simulation.
Journal ArticleDOI
Built-In Self-Test Techniques
TL;DR: The various linear-feedback shift register designs for pseudorandom or pseudoexhaustive input test pattern generation and for output response signature analysis are presented.
Book
VLSI Test Principles and Architectures: Design for Testability
TL;DR: A comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time to market and time-to-volume as mentioned in this paper.
Proceedings ArticleDOI
Minimized power consumption for scan-based BIST
TL;DR: The design modifications include some gating logic for masking the scan path activity during shifting, and the synthesis of additional logic for suppressing random patterns which do not contribute to increase the fault coverage.
References
More filters
Book
Shift register sequences
TL;DR: The Revised Edition of Shift Register Sequences contains a comprehensive bibliography of some 400 entries which cover the literature concerning the theory and applications of shift register sequences.
Proceedings ArticleDOI
A logic design structure for LSI testability
TL;DR: A logic design method that will greatly simplify problems in testing, diagnostics, and field service for LSI is described, based on two concepts that are nearly independent but combine efficiently and effectively.
Journal ArticleDOI
Controllability/observability analysis of digital circuits
TL;DR: The testability of a digital circuit is directly related to the difficulty of controlling and observing the logical values of internal nodes from circuit inputs and outputs, respectively as mentioned in this paper, and the testability is also related to how well the internal nodes can be controlled and observed.
Controllability/observability analysis of digital circuits
TL;DR: The testability of a digital circuit is directly related to the difficulty of controlling and observing the logical values of internal nodes from circuit inputs and outputs, respectively as discussed by the authors, and the testability is also related to how well the internal nodes can be controlled and observed.