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Proceedings ArticleDOI

Testing word oriented embedded RAMs using built-in self test

P. Baanen
- pp 196-202
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TLDR
The author presents a built-in self test method for word-oriented embedded static RAMs that gives a high fault coverage for digital faults, and can be parameterized to size, making automatic generation by a module compiler easy.
Abstract
The author presents a built-in self test method for word-oriented embedded static RAMs. Based on bit-oriented march tests, which are very suitable for self-test applications, word-oriented extensions are presented and analyzed for fault coverage. The self-test algorithm gives a high fault coverage for digital faults. Besides simple stuck-at faults, it detects transition faults and multiple-access faults. Also, all two-coupling faults between arbitrary pairs of cells are detected, so no knowledge of the physical placement of the cells is required. A prototype of the hardware implementation of the BIST method shows that the overhead, especially for large RAMs, is quite modest. The self-test hardware can be parameterized to size, making automatic generation by a module compiler easy. >

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Citations
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Journal ArticleDOI

A cellular automata based highly accurate memory test hardware realizing March C

TL;DR: T theory of 3 and 5-neighborhood CA, employed for the current application, has been developed to enhance the self-testability of memory test logic.
Proceedings ArticleDOI

A cellular automata based design of self testable hardware for March C

TL;DR: Hardware realization of March C is reported to enable high speed detection of faults in memories to enable a test structure self testable and reduce the overhead of bit by bit comparison of memory words, required in a conventional test structure.
Proceedings ArticleDOI

High Speed Hardware for March C

TL;DR: This work proposes hardware realization of March C- to enable efficient fault detection in memories to reduce the overhead of comparison that is required in a conventional test structure, to take decision on the faults in memory.
Proceedings ArticleDOI

A self testable hardware for memory

TL;DR: The proposed test hardware exhibits better efficiency in comparison to the state-of-the-art memory test designs, and reduces the test time while avoiding the bit by bit comparison of memory words, required in the conventional test designs.
Proceedings ArticleDOI

An efficient method for testing of L1 cache module in tiled CMPs architecture at low cost

TL;DR: A cost effective test structure to check a correctness of cache performance in chip multiprocessors (CMPs) is developed and the inability of the classical design to identify defective behavior of CMPs cache is overcome.
References
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Journal ArticleDOI

Macro Testing: Unifying IC And Board Test

TL;DR: A design for testability methodology for semicustom VLSI circuits is described by Philips, based on the partitioning of a design into testable macros, hence the term macro testing.
Journal ArticleDOI

Built-in Self Testing of Embedded Memories

TL;DR: Two algorithms are proposed for self-testing of embedded bedded RAMs, both of which can detect a large variety of stuck-at and non-stuck-at faults.
Journal ArticleDOI

An Improved Method for Detecting Functional Faults in Semiconductor Random Access Memories

TL;DR: This paper presents an efficient test procedure for the detection of simultaneously present functional faults in semi-conductor random access memories (RAM's) using 36N + 24N log2N operations, which is an improvement over existing techniques.
Journal ArticleDOI

Built-In Self-Testing RAM: A Practical Alternative

TL;DR: The article investigates the design of a built-in self-testing RAM as an economical way, in terms of silicon area overhead, to test memories more economical than the use of external testers.
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