Proceedings ArticleDOI
The Architecture of FDP FPGA Device
Jinmei Lai,Liguang Chen,Rui Tu,Man Wang,Yuan Wang,Jiarong Tong,Yabin Wang,Huowen Zhang +7 more
- pp 69-74
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TLDR
A novel FuDan programmable(FDP) FPGA device architecture was presented and the new 3-LUT based logic cell could increase logic density about 11% comparing with a traditional 4-input LUT.Abstract:
A novel FuDan programmable(FDP) FPGA device architecture was presented. The new 3-LUT based logic cell could increase logic density about 11% comparing with a traditional 4-input LUT. The uniquely hierarchy programmable routing fabrics and effective switch box could optimize the routing wire segments and make it possible for different length to connect directly and efficiently. The FDP FPGA device contains 1,600 programmable logic cells, 160 programmable IO Blocks and 16 K bits dual port block RAM IP Core. It was fabricated with SMIC 0.18 mum Logic 1P6M Salicide 1.8 V/3.3 V process, its die size is 6.1times6.6 mm2, with the package of QFP208.read more
References
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Book
Architecture and CAD for Deep-Submicron FPGAS
TL;DR: From the Publisher: Architecture and CAD for Deep-Submicron FPGAs addresses several key issues in the design of high-performance FPGA architectures and CAD tools, with particular emphasis on issues that are important for FPG as implemented in deep-submicron processes.
Journal ArticleDOI
FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs
Jason Cong,Yuzheng Ding +1 more
TL;DR: A theoretical breakthrough is presented which shows that the LUT-based FPGA technology mapping problem for depth minimization can be solved optimally in polynomial time.
Journal ArticleDOI
The effect of LUT and cluster size on deep-submicron FPGA performance and density
Elias Ahmed,Jonathan Rose +1 more
TL;DR: This paper revisits the field-programmable gate-array (FPGA) architectural issue of the effect of logic block functionality on FPGA performance and density, and experimentally determines the relationship between the number of inputs required for a cluster as a function of the LUT size and cluster size.
Proceedings ArticleDOI
FPGA Downloading Circuit Design and Implementation
TL;DR: The way of loading the bit file into the FPGA chip, which has been taped out with SMIC 0.18mum CMOS process this year, and MODELSIM is used to verify the design before and after the layout is generated.
Proceedings ArticleDOI
Fpga routing architecture optimization
TL;DR: A versatile SB model with 4 sides is presented, so versatile that it can cover various kinds of 4-side SB architectures in a 2-D FPGA and a new segment distribution method in segmented architecture is proposed, which can greatly reduce circuits delay.