Journal ArticleDOI
The turn model for adaptive routing
TLDR
This paper presents a model for designing wormhole routing algorithms based on analyzing the directions in which packets can turn in a network and the cycles that the turns can form, which produces routing algorithms that are deadlock free, livelockfree, minimal or nonminimal, and highly adaptive.Abstract:
This paper presents a model for designing wormhole routing algorithms. A unique feature of the model is that it is not based on adding physical or virtual channels to direct networks (although it can be applied to networks with extra channels). Instead, the model is based on analyzing the directions in which packets can turn in a network and the cycles that the turns can form. Prohibiting just enough turns to break all of the cycles produces routing algorithms that are deadlock free, livelock free, minimal or nonminimal, and highly adaptive. This paper focuses on the two most common network topologies for wormhole routing, n-dimensional meshes and k-ary n-cubes without extra channelsread more
Citations
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Journal ArticleDOI
A survey of research and practices of Network-on-chip
TL;DR: The research shows that NoC constitutes a unification of current trends of intrachip communication rather than an explicit new alternative.
Journal ArticleDOI
The odd-even turn model for adaptive routing
TL;DR: Simulation results show that the even adaptiveness provided by the odd-even turn model makes message routing less vulnerable to nonuniform factors such as hot spot traffic and results in a smaller fluctuation of the network performance with respect to different traffic patterns.
Journal ArticleDOI
HERMES: an infrastructure for low area overhead packet-switching networks on chip
TL;DR: The state of the art in networks on chip is reviewed, an infrastructure called Hermes is described, targeted to implement packet-switching mesh and related interconnection architectures and topologies and the design validation of the Hermes switch is presented.
Proceedings ArticleDOI
DyAD - smart routing for networks-on-chip
Jingcao Hu,Radu Marculescu +1 more
TL;DR: A new routing technique which judiciously switches between deterministic and adaptive routing based on the network's congestion conditions is envisioned, and the effectiveness of DyAD is evaluated by comparing it with purely deterministicand adaptive routing schemes under different traffic patterns.
Proceedings ArticleDOI
Regional congestion awareness for load balance in networks-on-chip
TL;DR: Regional Congestion Awareness (RCA) is proposed, a lightweight technique to improve global network balance that informs the routing policy of congestion in parts of the network beyond adjacent routers.
References
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Journal ArticleDOI
Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
TL;DR: In this article, a deadlock-free routing algorithm for arbitrary interconnection networks using the concept of virtual channels is presented, where the necessary and sufficient condition for deadlock free routing is the absence of cycles in a channel dependency graph.
Journal ArticleDOI
A survey of wormhole routing techniques in direct networks
Lionel M. Ni,Philip K. McKinley +1 more
TL;DR: The properties of direct networks are reviewed, and the operation and characteristics of wormhole routing are discussed in detail, along with a technique that allows multiple virtual channels to share the same physical channel.
Journal ArticleDOI
The Torus Routing Chip
TL;DR: The torus routing chip (TRC) is a selftimed chip that performs deadlock-free cut-through routing ink-aryn-cube multiprocessor interconnection networks using a new method of deadlock avoidance called virtual channels.
Journal ArticleDOI
Performance analysis of k-ary n-cube interconnection networks
TL;DR: In this paper, the authors derived expressions for the latency, average case throughput, and hot-spot throughput of k-ary n-cube networks with constant bisection that agree closely with experimental measurements.
Journal ArticleDOI
The directory-based cache coherence protocol for the DASH multiprocessor
TL;DR: The design of the DASH coherence protocol is presented and how it addresses the issues of correctness, performance and protocol complexity are discussed and compared to the IEEE Scalable Coherent Interface protocol.