Proceedings ArticleDOI
Using BIST control for pattern generation
Gundolf Kiefer,Hans-Joachim Wunderlich +1 more
- pp 347-355
TLDR
A deterministic BIST scheme is presented which requires less hardware overhead than pseudo-random BIST but obtains better or even complete fault coverage at the same time.Abstract:
A deterministic BIST scheme is presented which requires less hardware overhead than pseudo-random BIST but obtains better or even complete fault coverage at the same time. It takes advantage of the fact that any autonomous BIST scheme needs a BIST control unit for indicating the completion of the self-test at least. Hence, pattern counters and bit counters are always available, and they provide information to be used for deterministic pattern generation by some additional circuitry. This paper presents a systematic way for synthesizing a pattern generator which needs less area than a 32-bit LFSR for random pattern generation for all the benchmark circuits.read more
Citations
More filters
Proceedings ArticleDOI
A mixed mode BIST scheme based on reseeding of folding counters
TL;DR: The proposed scheme relies on a new type of test pattern generator which resembles a programmable Johnson counter and is called folding counter and outperforms previously published approaches based on the reseeding of LFSRs or Johnson counters.
Proceedings ArticleDOI
Two-dimensional test data compression for scan-based deterministic BIST
TL;DR: A novel architecture for scan-based mixed mode BIST relies on a two-dimensional compression scheme, which combines the advantages of known vertical and horizontal compression techniques.
Journal ArticleDOI
Application of deterministic logic BIST on industrial circuits
TL;DR: Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100 K gates with 10,000 test patterns, at a total area cost for BIST hardware of typically 5–15%.
Journal ArticleDOI
Bit-fixing in pseudorandom sequences for scan BIST
Nur A. Touba,Edward J. McCluskey +1 more
TL;DR: A low-overhead scheme for achieving complete (100%) fault coverage during built-in self test of circuits with scan is presented and experimental results indicate that complete fault coverage can be obtained with low hardware overhead.
Proceedings ArticleDOI
Low hardware overhead scan based 3-weight weighted random BIST
TL;DR: Experimental results show that the proposed BIST schemes can attain 100% fault coverage for all of benchmark circuits with drastically reduced test sequence lengths, achieved at low hardware cost even for benchmark circuits that have large number scan inputs.
References
More filters
Book
Digital Systems Testing and Testable Design
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Proceedings ArticleDOI
Combinational profiles of sequential benchmark circuits
F. Brglez,D. Bryan,K. Kozminski +2 more
TL;DR: A set of 31 digital sequential circuits described at the gate level that extend the size and complexity of the ISCAS'85 set of combinational circuits and can serve as benchmarks for researchers interested in sequential test generation, scan-basedtest generation, and mixed sequential/scan-based test generation using partial scan techniques.