Why keep drain source in stacked fet at same potential?
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In stacked FETs, maintaining the drain and source at the same potential is crucial to prevent unwanted effects like negative differential resistance (NDR) and to optimize device performance. Additionally, in the context of FinFETs, the introduction of acceptor-like and donor-like traps in the oxide/channel interface can impact the device characteristics differently, affecting the on-state and off-state behavior. Furthermore, in the case of SNSH-FETs, optimizing the structure by incorporating an extra channel with a supersteep retrograde doping profile helps alleviate parasitic capacitance and leakage, leading to enhanced drive current and improved RF/analog performance. Overall, maintaining the drain-source at the same potential in stacked FETs is essential for achieving desired device characteristics and performance enhancements.
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| Papers (5) | Insight |
|---|---|
7 Citations | To reduce capacitance and leakage, a source/drain-on-insulator (SDOI) structure is used in stacked FETs, maintaining the drain and source at the same potential for improved performance. |
| In a stacked FET, keeping the drain and source at the same potential helps optimize analog/RF performance by reducing negative differential resistance and enhancing device characteristics for improved functionality. | |
Patent 17 Jun 2010 16 Citations | In the context of the paper, epitaxial source/drain contacts are aligned to gates to maintain structural integrity, enhancing device performance by keeping the drain and source at the same potential. |
| In a dual core source/drain GAA FinFET, keeping the drain and source at the same potential enhances device performance by optimizing doping concentrations for improved electrical parameters. | |
| In a stacked FET, keeping the drain and source at the same potential helps optimize analog/RF performance by reducing negative differential resistance and enhancing device suitability for various applications. |
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