Showing papers on "Adder published in 1977"

High speed combinatorial digital multiplier

Abstract: This disclosure relates to a high speed combinatorial 8 by 8 digital multiplier suitable for implementation on a single semiconductor chip including an encoder for implementing the Modified Booth Algorithm to encode the eight multiplier digits. The encoder includes five subsections which generate a plurality of control signals. Each of the plurality of control signals is inputted into a separate one of five multiplexor circuits each of which also receives inputs representative of eight multiplicand bits in accordance with implementation of the Modified Booth Algorithm. Each of the five multiplexer circuits provides a plurality of outputs, each of the pluralities of outputs representing a separate partial product of the multiplier and multiplicand inputs. The partial products are inputted to an array of carry-save adders. The final stage of the adder network includes a carry-look-ahead adder which produces sixteen outputs which represent the product of the multiplier and the multiplicand. The multiplier includes circuitry for permitting encoding of the multiplier inputs in either binary unsigned or in two's compliment form. A multiplier mode control input controls whether the multiplier inputs are operated upon as two's compliment or as unsigned binary numbers. Similarly, a mode control input to circuitry which generates the multiplexer inputs representative of the multiplicand also controls whether the multiplicand inputs are operated upon as two's compliment numbers or as unsigned binary numbers. The mode of the multiplier inputs and multiplicand inputs can be independently controlled, so that mixed signed and unsigned representations of the multiplier and multiplicand, respectively, can be utilized.

Floating point data processor having fast access memory means

Abstract: A digital data processor includes a plurality of memory registers, a floating point adder and a floating point multiplier intercoupled by a plurality of simultaneously operable parallel buses facilitating multiple parallel operations during one clock cycle or instruction. The floating adder and multiplier each include a number of stages separated by intermediate temporary storage registers which receive the partial results of a computation for use by the next stage during the next clock period. Floating point additions, multiplications and other arithmetic and logical results are produced during each clock cycle. Memory registers comprise a data pad having a plurality of selectable stack registers and means for writing information into said data pad during one clock cycle for retrieval during the next clock cycle.

Comment on the Sequential and Indeterminate Behavior of an End-Around-Carry Adder

Abstract: The sequential and indeterminate behavior of an end-around-carry (EAC) adder is examined. This behavior is commonly overlooked in the literature. Design modifications to impose determinism are provided. These modifications also eliminate the troublesome negative zero found in the one's complement number system.

Tree Realizations of Iterative Circuits

Abstract: It is shown how any combinational function that can be described by a flow table—or equivalently—is realizable in iterative form—can be realized in tree form. The propagation delay is then proportional to the logarithm of n, the number of inputs, while the logic complexity is a linear function of n. These results are related to various implementations of high-speed binary adders and a proposed new high-speed adder circuit.

Majority decision device

Abstract: A majority decision circuit is disclosed having reduced shift register bit capacity and the capability of providing a majority decision for varying repetition number. A full adder is used and the data words are applied serially to the carry input. The output is applied via shift registers back to the input, and a bias value is applied to the second input. The carry-out bits of the adder represent the majority decision.

System for generating tone source waveshapes

Abstract: The system comprises a frequency number memory device for storing information regarding the frequencies of respective tones, a keyboard switch for reading out frequency number information corresponding thereto from the memory device, an address generator including an adder for adding a predetermined number of the frequency number information thereby producing an address signal consisting of plural bits, address composers for processing the bits of the address signal and thereby composing digital tone signals constituting a saw-tooth, square and triangular waveshape, and digital-analog converters for converting the digital tone signals into analog tone signals, which are thereafter used to synthesize waveshapes of any tone.

Single line propagation adder and method for binary addition

Abstract: A propagation line adder may be fabricated by replicating a unit circuit along a single sense propagation path. Each unit circuit corresponds to a bit of the same order of magnitude of the binary addends. Selected segments of the sense propagation path are set at a specified logical potential value and are coupled according to control signals generated within the unit circuit in response to the addend bits. A sense amplifier, coupled to each segment of the sense propagation paths, detects the state on corresponding segments of the sense propagation path. The propogation line adder implements an algorithm which produces the binary sum of two numbers by complementing the exclusive-or function of the addends according to a shifted product function. The shifted product function includes a carry-in bit as its lowest order bit.

Realization of a multivalued integrated injection logic (MI/sup 2/L) full adder

Abstract: A multivalued integrated injection logic scheme and its application to the realization of a full adder is described in this correspondence. The integrated full adder is implemented and fabricated using V-groove isolated I/SUP 2/L technology. Results obtained on the experimental structures indicate that the multivalued full adder offers an increase in functional density while retaining approximately the same area x delay product as a binary full adder at identical power levels.

Digital charge-coupled logic (DCCL)

Abstract: A new method of implementing digital logic functions is presented. The method is based on the use of charge-coupled devices in pipeline configurations and results in a very high functional density and an extremely low power dissipation. The authors show how various logic functions such as OR, AND, INVERT, and charge refresh are performed. The operation of a DCCL full-adder is compared with another configuration that uses cascaded dual half-adders and a carry-OR. A floating-gate is required as a binary switch in any function that requires binary inversion such as an exclusive-OR. The switching range of the floating-gate is derived as a function of the gate area, the size of the input charge packet and the extraneous capacitances. The implementation of DCCL pipeline arithmetic is discussed. An 8/spl times/8 multiplier and a 16+16 adder pipeline array now being produced are described. The power dissipation and package density of DCCL are compared with PMOS, NMOS, CMOS, and I/SUP 2/L devices in full-adder configurations and in various size arithmetic arrays. The authors conclude with a description of the present status of the technology and some projections for future uses.

Electronic musical instrument

Abstract: PURPOSE:To readily and surely obtain signals of waveforms corresponding to respective intervals by subsequently determining the sampling points of the waveforms for the same intervals with the values subsequently integrating the sampling intervals being read out from memories. CONSTITUTION:Sampling intervals X1, X2,...X88 for respective intervals are converted to binary codes of respectively specified bit numbers and written in respective words of 88 of the ROM 71 in a retrieval circuit 7 and the respective intervals are determined according to the reference frequencies of the respective intervals. The words of 88 of RAM 72 are also written with the sampling positions of the waveforms for momentary intervals in correspondence to the respective intervals as binary codes of specified bit numbers. When power source is turned on, the word for the interval A0 of both memories is addressed and X1 is read out from the ROM 71 and 0 from the RAM 72 respectively. The output of an adder 73 then becomes X1, which is stored in a buffer 74. In a DA converter 74, one step of the pitch corresonding to the value of X1 of the staircase signals is formed. Thereby, the signals of the waveforms corresponding to the respective intervals may be surely obtained.

Musical note oscillator

Abstract: The disclosure describes an improved digital oscillator for use in an electronic musical system capable of converting electrical tone signals into corresponding sound waves. The oscillator includes an adder, accumulator and multiplexer for selectively transmitting either a divisor number or increment number to the adder. The oscillator cyclically performs incrementing operations by using the increment number over a variable range established by the divisor number at the beginning of each cycle. When the modulus of the adder is exceeded, the adder generates a carry pulse and a remainder. The divisor is then added to the remainder before the incrementing operations begin again. A digital calculator automatically calculates the proper values of the increment and divisor numbers so that the carry pulses occur at a predetermined frequency.

High speed binary and binary coded decimal adder

Abstract: A high speed binary and binary coded decimal adder which employs a plurality of partial adders and a carry look ahead circuit and is adapted to effect a binary coded decimal addition with only one processing of the adder. The partial adders are each composed of a half adder for generating a bit generate signal and a bit propagate signal, a binary mode carry look ahead input signal generator circuit part, a binary coded decimal mode carry look ahead input signal generator circuit part, an intermediate adder part and a full adder part. The high speed binary and binary coded decimal adder is capable of providing the result of an addition at a speed corresponding to six to seven logical stages.

Variable function generator

Abstract: A fully digitalized function-of-time generator suitable for use as a tone envelope generator in a digital electronic musical instrument, comprising: a clock pulse generator for generating a clock pulse at a selectable rate; a gate enabled at each arrival of the clock pulse; a single-stage binary shift register for successively shifting out its contents as a digital word representing the instantaneous values of a desired function of time synchronously with the clock pulse; a digital subtractor; a digital multiplier; and a digital adder, all of these members being interconnected to each other to be operative so that the output of the register is subtracted from a first set value representing a digital word, the resulting difference being multiplied by a second set value representing a digital word, the resulting product being added to the output of the register via the gate, so that the resulting sum is loaded into the register. Thus, the contents of the register approaches progressively toward the first set value, and finally becomes in agreement therewith. Thus, this musical instrument can produce a musical tone rich in expression and imparted with desired tone envelope characteristic, by appropriate choice of one or more of the first and the second values and the rate of the clock pulse.

Phase locked loop frequency synthesizer using digital modulo arithmetic

Abstract: A reference source of digital pulses of a first frequency f 1 is coupled to the input of a frequency synthesizer which is capable of providing a second frequency f 2 output signal. The second frequency is related to the first frequency by a predetermined, rational fraction (e.g., as f 2 = (M/N)f 1 ). The synthesizer includes a phase control unit comprising an adder by way of which a first number N is added each sample period to a remainder, the sum output of the adder being operated upon modulo a second number M, e.g., by dividing by M and discarding a resultant quotient to obtain a remainder. The remainder, having a value between zero and M-1, is compared to a prefixed signal, illustratively the largest integer in M/2. If the remainder is less than the prefixed signal, a first logic state control signal is provided to a control system; else a second logic state signal is so provided. The alternation between the first and second logic states is such that M pulses of the second frequency occur for every N pulses of the first frequency. Thereby, the second frequency is synthesized responsive to the first.

Bit error rate performance monitor units in digital transmission links

Abstract: A bit error performance monitor in which the input signal is equally shared by two substantially identical monitors whose outputs in turn are connected to an adder. The output of the adder passes through a divider-by-2 to a counter.

Note frequency generator for a polyphonic tone synthesizer

Abstract: A frequency generator for a keyboard operated electronic music instrument using a single master clock source for selectively producing all the notes of the musical scale. A set of frequency numbers corresponding to each of the notes of a diatonic scale are stored in a memory. A frequency number is selected from the stored numbers according to the note to be generated when a key on a keyboard is activated, the selected number being applied to an adder-accumulator periodically at the master clock rate for incrementing the contents of the accumulator. Overflow pulses from the adder-accumulator shift amplitude values sequentially from a set of values stored in a shift register through an adder to a digital-to-analog converter. The adder modifies the amplitude values by applying a fractional part of the incremental difference between each value and the next value in the sequence to the adder. The fractional amount is determined by the content of the adder-accumulator and changes with each master clock pulse.

Device for automatically braking the wheel of a vehicle

Abstract: The invention relates to a device for automatically braking the wheel of a vehicle, in which a hydraulic brake controlled by a mechanical member is associated with the wheel and is controlled by an electrohydraulic servovalve receiving an electric signal for controlling a transmitter charged with converting the displacements of the mechanical member into electric signals, wherein, between the transmitter and the servovalve, the device comprises a switch which, for a first position, directly connects the transmitter and the servovalve and which, for a second position, connects the output of the transmitter to one of the inputs of a first adder whose output is connected to the servovalve, the other input of this first adder being connected to the output of an automatic braking signal generator. The invention is more particularly applied to the braking of aircraft.

Multivalued integrated-injection-logic (MI2L) full adder

Abstract: A multivalued integrated-injection-logic full adder is described. Results obtained on the experimental structure indicate that the multivalued I2L full adder offers an increase in functional density while retaining approximately the same area–delay product as a binary full adder.

System for the digital clamping of periodic, binary encoded signals

Abstract: A binary encoded signal which is to be clamped at a desired binary value is simultaneously applied to a digital subtractor and a digital adder. The digital subtractor subtracts the difference between the desired binary value and the value of the binary encoded signal. The resulting difference is applied to a storage flip-flop circuit having a switching pulse input which receives a periodic signal. The flip-flop transfers the last received difference until the periodic signal is received causing it to transfer the latest received difference. A binary adder adds the output of the storage flip-flop to the binary encoded signal. This results in a corrected clamped binary encoded signal.

Adaptive method of and means for recovering digital signals

Abstract: An incoming data stream in the output of a demodulator and its derivative in the output of a differentiator are passed by respective sampling gates to a pair of equalizers operating by recursive filtration. The optimized data pulses issuing from the first equalizer are quantized and, after storage in a shift register, are algebraically combined in a first adder with a reference signal x from that equalizer representing the vector sum of weighted data pulses from a succession of N preceding clock cycles; a resulting error signal e n is delivered to three cumulative multipliers forming part of three feedback loops which supply an optimized phase signal ζ to the demodulator, an optimized timing signal τ to the sampling gates and an optimized gain coefficient K to the equalizers. These three multipliers respectively receive the reference signal x from the first equalizer, an optimized differential signal dx/dτ from the second equalizer and an updating signal z from the first equalizer. A further cumulative multiplier forms part of a fourth feedback loop delivering an optimized channel coefficient G to the equalizers, this latter loop including a second adder which synthesizes another error signal e' from the incoming data pulses z and from the complex product G·x produced by the last-mentioned multiplier. Each feedback loop includes a selective delay circuit effective only during an operating phase, in contrast to an acquisition phase during which the first adder receives a locally generated test signal in lieu of the quantized data pulses.

Digital beam former

Abstract: PURPOSE:To make it possible to generate a received beam with random characteristics easily and economically with high precision by applying digital signal processing technique. CONSTITUTION:Input signals of K channels are sampled at a constant rate and converted by A-D converters 221-22k into digital codes, which are written in input memories 231-23k. On the other hand, data block consisting of N sampled values read from memories 231-23k are sent to FFTs processors 241-24k, where the next Fourier transformation comes into effect to calculate complex spectrums as many as N/2. Next, transfer functions in table memories 261-26k are multiplied by complex multipliers 251-25k by the above-mentioned spectrums as to every frequency component and the results are added by complex adder 27 covering all channels; and the results are Fourier-transformed reversely by FFT processor 28 and the result is written in output memory 29. The data are sequentially read out at a rate equal to the sampling rate of the input side.

One's complement subtractive arithmetic unit utilizing two's complement arithmetic circuits

Abstract: The one's complement subtractive arithmetic unit comprises a parallel adder with a connection for providing an end-around carry, from the carry output of the most significant stage to the carry input of the least significant stage. The parallel adder is implemented utilizing multiple bit LSI ALU chips or microprocessor slices that provide group propagate and generate indication signals. Carry look-ahead chips responsive to the group propagate and generate indication signals provide a fast carry arrangement for the arithmetic unit. Circuitry is included to detect when all of the carry propagate indicators are on for providing a signal to the carry input of the parallel adder resulting in the equivalent performance of a one's complement subtractive arithmetic unit.

Gunn effect high-speed carry finding device for 8-bit binary adder

Abstract: A new type of Gunn effect gate device was reported by us earlier and demonstrated in the form of a 4 bit gate device(1). The 4 bit gate device consisted of four cascaded inhibitors, each inhibitor being an integration of a Schottky electrode-triggered Gunn device and a m.e.s.f.e.t. The device had the high-speed property of the Gunn device and the stability of operation inherent to the m.e.s.f.e.t. operated in an on-off mode. This paper reports the application of such inhibitors to a high-speed carry finding device. The inhibitors have been improved in construction and operation in many ways. The most important improvement is the attachment of a memory function to the inhibitor whereby the output signal is held for any long time desired even the input signal comes in the form of a pulse of short duration. The memory makes use of the accumulation of excess electrons on the Schottky trigger electrode. Such an arrangement has also brought a remarkable improvement in the anode voltage margin.

Automatic Target Hand-Off Using Correlation Techniques

Abstract: : The problem of automatic hand-off of a target from a precision pointing and tracking system (PTS) to an imaging missile seeker is considered in this report. The approach taken is to search for the target in the seeker field of view (FOV) using the PTS video as a reference. When the target is located, the seeker line of sight is adjusted automatically such that the target is at the center of its FOV at which point the seeker tracker can lock on to the target. Location of the target in the seeker FOV can best be accomplished using correlation techniques. The approach taken is to consider the most accurate but yet most costly in computation time and hardware requirements. Tradeoffs are then considered in order to obtain a real-time correlator (i.e., one which can compute the correlation surface at the rate of the incoming live video from the seeker). The effect of these trade-offs on correlation accuracy and other system performance criteria is given. A correlation algorithm is chosen and an implementation of this algorithm is given. An alternate implementation using an analog adder rather than a digital adder tree is recommended.

Digitally encoded top octave frequency generator

Abstract: A LSI (large scale integrated circuit) device is disclosed which generates 12 output frequencies related to each other by a multiple of the twelfth root of two from a common time base without the use of parallel divider or shift register strings. The output frequencies comprise the top octave, or a multiple thereof, of the frequencies of an electronic musical instrument. A binary counter serves as a common time base and encodes each wave form period in a form of a binary code. A binary processing circuit associated with each output frequency stores the count position of the next desired wave form transition and updates the stored code after each transition has occurred. The binary processing circuitry comprises a latch circuit, a binary full adder or ROM (read only memory), a digital comparator or ROM, and a J-K flip-flop circuit. The outputs can be easily modified in both actual frequency and waveform symmetry.

Device for automatic dimension control of extruded blanks

Abstract: A device for automatic dimension control of extruded blanks comprises a means for measuring the blank width, having its output connected to an input of a third adder whose second input is connected to a means for presetting the blank dimensions and whose output is connected to the input of an amplifier-converter, a motor for driving the screw of an extruder, with an extruder screw rpm sensor, a motor for driving a drawing-off device, with a draw-off speed sensor, a means for presetting the draw-off speed, a first adder whose inputs are connected, respectively, to a means for presetting the extruder screw rpm and to said extruder screw rpm sensor and whose output is connected, via a first amplifier, to said screw drive motor, a second adder whose first input is connected to said draw-off speed sensor and whose output is connected, via a second amplifier, to said drawing-off device drive motor, a nonlinearity unit, a compensator unit, and a fourth adder whose first input is connected to the output of the compensator unit having its input connected to the extruder screw rpm sensor, the second input of the nonlinearity unit being connected to the extruder screw rpm sensor and receiving a bias voltage, while the first input of the nonlinearity unit is connected to the output of the fourth adder, the output of the amplifier-converter is connected to the second input of the fourth adder, and the outputs of the nonlinearity unit and draw-off speed presetting means are connected to the first input of the third adder via a switch.

New magnetic scaler used as universal arithmetic module for pulse-train signal processing

Abstract: This paper describes a new magnetic decimal scaler as a universal arithmetic module (UAM) realized by expanding the function of the multi-level magnetic scaler. In order to implement pulse-train signal processing systems, three arithmetic operations (addition, multiplication and delay) are required. The proposed UAM has adder, multiplier and delay functions, all in one. So the pulse-train signal processing systems can be implemented by using only UAM's as a basic building block. This results in high reliability and simplicity with respect to the operation and construction of the systems, as compared with the case using commercially available binary-circuits.

Direct-coupled Josephson full adder

Abstract: We describe a one-bit full adder circuit constructed from direct-coupled Josephson logic elements. The basic gate, which can perform various logic functions, consists of two Josephson junctions and two resistors connected in a loop. Switching the junctions into the finite-voltage state diverts the bias current into a parallel output line, which is directly coupled through the junctions of successive logic elements. The adder is constructed with a 100 μm basic linewidth and 25 μm square tin tunnel junctions. It operates under all input data conditions with an add time of about 1 nS and a power dissipation of 1 μW per gate.

Statistical analyzer of working process parameters of machinery

Abstract: The proposed statistical analyzer comprises a converter of physical quantities to voltage, connected to direct inputs of comparators whose number corresponds to that of voltage quantization levels. The analyzer also includes adders. One input of each adder is connected to the output of a standard voltage generator; the output of each adder is connected to the inverting input of a comparator. The output of each comparator is connected to the second input of each adder corresponding to a quantization level which is one level below the quantization level corresponding to this comparator. The statistical analyzer of this invention is marked by a high accuracy and reliability and makes it possible to obtain a bar chart of any working process parameter of a machine.

High speed pulse interpolator

Abstract: A D.D.A. (Digital Differential Analyzer) for pulse interpolation having a memory counter with more than two bit positions for counting the number (m) of input instruction pulses in each interpolation cycle, a second counter for receiving the content of the memory counter, and an auxiliary adder for obtaining m multiple of the content of the integrand register in the D.D.A. system. The output of the auxiliary adder instead of the output of the integrand register is applied to an interpolation adder. Thus, the pulse interpolator can operate correctly even when more than two input instruction pulses are generated within a single interpolation cycle.